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16-bit, 160 msps 2x/4x/8x interpolating dual txdac+ ? d/a converter ad9777 rev. c in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th ir d par t ies th a t m a y r e su l t f r o m i t s use . s p e c i f ica t io n s su bj e c t t o c h an g e w i th o u t n o ti c e . n o l i c e n s e i s g r an t e d b y imp l ic a t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g d e v i c e s . t r adem ar ks and r e g i st e r ed tr ad ema r ks ar e the p r o p er t y of the i r r e sp e c t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2006 analog devices, inc. all rights reserved. fea t ures 16-bit resoluti on, 160 msps/400 msps inpu t/output da ta r a te s e lec t able 2/ 4 /8 int e rpola t ing filt er p r ogr a mmable channel gain a n d off s et a d jus t men t f s /4, f s /8 digital qua d r a tur e m o dula tion c a pabilit y dir e c t if tr ans m ission mode f o r 70 mhz + ifs enables image r e jec t ion ar chit ec tur e f u lly c o mpa t ible spi? por t ex c e llent ac pe r f ormanc e sfdr ?7 3 db c @ 2 m hz t o 35 mhz w c dma a c pr 71 db @ if = 19 .2 mhz in t e rnal pll clock mu ltiplier s e lec t able int e rnal clock divi d e r v e rsa t ile clock input d i ff er entia l /single - ended sine wa v e or t t l/cmos/l v pecl c o mpa t ible v e rsa t ile input da ta in ter f ac e t w os c o mplemen t /str aigh t bi nar y da ta c o di ng dual-por t or si ngle -por t in t e rlea v e d input da ta single 3.3 v s u p p ly oper a t ion p o w e r dissipa t ion: t y pic a l 1.2 w @ 3.3 v o n - c hip 1.2 v ref e renc e 80-lea d thin quad fla t pack age , e x posed pad ( t qfp_ep ) applic a t io ns c o mmunic a tions a n alog qua d r a tur e modula t i on ar chit ec tur e 3g, multic arrier gsm, t d ma , cdma sy s t ems b r o a dband wireless , po int-to - p o i nt micr owa v e r a dio s instrumen t a t ion/a t e func ti on a l bl ock di a g r a m 16 16 16 /2 16 16 16 16 16 /2 /2 /2 ad9777 data assembler i latch q latch mux control spi interface and control registers half-band filters also can be configured for zero stuffing only * i and q noninterleaved or interleaved data 16 16 clock out write select half- band filter1* filter bypass mux image rejection/ dual dac mode bypass mux i/q dac gain/offset registers half- band filter2* half- band filter3* cos idac idac vr ef ioffset gain dac differential clk offset dac cos i out prescaler pll clock multiplier and clock divider phase detector and vco sin sin f dac /2, 4, 8 ( f dac ) 02706-001 figure 1.
ad9777 rev. c | page 2 of 60 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 4 product highlights ....................................................................... 4 specifications ..................................................................................... 5 dc specifications ......................................................................... 5 dynamic specifications ............................................................... 6 digital specifications ................................................................... 7 digital filter specifications ......................................................... 8 absolute maximum ratings ............................................................ 9 thermal characteristics .............................................................. 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 ter mi nolo g y .................................................................................... 12 typical performance characteristics ........................................... 13 mode control (via spi port) ..................................................... 18 register description ................................................................... 20 functional description .................................................................. 22 serial interface for register control ........................................ 22 general operation of the serial interface ............................... 22 instruction byte .......................................................................... 23 r/w .............................................................................................. 23 n1, n0 .......................................................................................... 23 a4, a3, a2, a1, a0 ..................................................................... 23 serial interface port pin descriptions ..................................... 23 msb/lsb transfers ..................................................................... 23 notes on serial port operation ................................................ 25 dac operation ........................................................................... 25 1r/2r mode ................................................................................ 26 clock input configuration ................................................... 26 programmable pll .................................................................... 27 power dissipation ....................................................................... 29 sleep/power-down modes ........................................................ 29 two port data input mode ....................................................... 29 pll enabled, two-port mode .................................................. 30 dataclk inversion .................................................................. 30 dataclk driver strength ....................................................... 30 pll enabled, one-port mode .................................................. 30 oneportclk inversion ......................................................... 31 oneportclk driver strength .............................................. 31 iq pairing .................................................................................... 31 pll disabled, two-port mode ................................................. 31 pll disabled, one-port mode ................................................. 32 digital filter modes ................................................................... 32 amplitude modulation .............................................................. 32 modulation, no interpolation .................................................. 34 modulation, interpolation = 2 ............................................... 35 modulation, intermodulation = 4 ......................................... 36 modulation, intermodulation = 8 ......................................... 37 zero stuffing ............................................................................... 38 interpolating (complex mix mode) ........................................ 38 operations on complex signals ............................................... 38 complex modulation and image rejection of baseband signals .......................................................................................... 39 image rejection and sideband suppressions of modulated carriers ........................................................................................ 41 applying the output configurations ........................................... 46 unbuffered differential output, equivalent circuit ............. 46 differential coupling using a transformer ............................ 46 differential coupling using an op amp ................................ 47 interfacing with the ad8345 quadrature modulator ........... 47 evaluation board ............................................................................ 48 outline dimensions ....................................................................... 58 ordering guide .......................................................................... 58
ad9777 rev. c | page 3 of 60 revision history 1/06 rev. b to rev. c updated formatting .........................................................universal changes to figure 32 .................................................................... 22 changes to figure 108 .................................................................. 54 updated outline dimensions ..................................................... 58 changes to ordering guide......................................................... 58 6/04data sheet changed from rev. a to rev. b. changes to dc specifications ....................................................... 5 changes to absolute maximum ratings...................................... 8 changes to dac operation section........................................... 25 changes to figure 49, figure 50, and figure 51........................ 29 changes to the pll enabled, one-port mode section............ 30 changes to the pll disabled, one-port mode section........... 32 changes to the ordering guide .................................................. 57 updated the outline dimensions ............................................... 57 3/03data sheet changed from rev. 0 to rev. a. edits to features .............................................................................. 1 edits to dc specifications ............................................................. 3 edits to dynamic specifications.................................................... 4 edits to pin function descriptions............................................... 7 edits to table i ............................................................................... 14 edits to register descriptionaddress 02h section ............... 15 edits to register descriptionaddress 03h section ............... 16 edits to register descriptionaddress 07h, 0bh section...... 16 edits to equation 1........................................................................ 16 edits to msb/lsb transfers section........................................... 18 changes to figure 8 ...................................................................... 20 edits to programmable pll section........................................... 21 added new figure 14.................................................................... 22 renumbered figures 15 to 69...................................................... 22 added two-port data input mode section............................... 23 edits to pll enabled, two-port mode section ........................ 24 edits to figure 19 ......................................................................... 24 edits to figure 21 .......................................................................... 25 edits to pll disabled, two-port mode section ....................... 25 edits to figure 22 .......................................................................... 25 edits to figure 23 .......................................................................... 26 edits to figure 26a ........................................................................ 27 changes to figures 53 and 54...................................................... 38 edits to evaluation board section .............................................. 39 changes to figures 56 to 59......................................................... 40 replaced figures 60 to 69 ............................................................ 42 updated outline dimensions...................................................... 49 7/02revision 0: initial version
ad9777 rev. c | page 4 of 60 general description the ad9777 1 is the 16-bit member of the ad977x pin compatible, high performance, programmable 2/4/8 interpolating txdac+ family. the ad977x family features a serial port interface (spi) that provides a high level of programmability, thus allowing for enhanced system level options. these options include selectable 2/4/8 interpola- tion filters; f s /2, f s /4, or f s /8 digital quadrature modulation with image rejection; a direct if mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single- port or dual-port data interface. the selectable 2/4/8 interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the txdac+ familys pass-band noise/distortion performance. the independent channel gain and offset adjust registers allow the user to calibrate lo feedthrough and sideband suppression errors associated with analog quadrature modulators. the 6 db of gain adjustment range can also be used to control the output power level of each dac. the ad9777 features the ability to perform f s /2, f s /4, and f s /8 digital modulation and image rejection when combined with an analog quadrature modulator. in this mode, the ad9777 accepts i and q complex data (representing a single or multicarrier wave- form), generates a quadrature modulated if signal along with its orthogonal representation via its dual dacs, and presents these two reconstructed orthogonal if carriers to an analog quadrature modulator to complete the image rejection upconversion process. another digital modulation mode (that is, the direct if mode) allows the original baseband signal representation to be fre- quency translated such that pairs of images fall at multiples of one-half the dac update rate. the ad977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. an internal pll clock multiplier is included and generates the necessary on-chip high frequency clocks. it can also be disabled to allow the use of a higher performance external clock source. an internal programmable divider simplifies clock generation in the converter when using an external clock source. a flexible data input interface allows for straight binary or twos comple- ment formats and supports single-port interleaved or dual-port data. dual high performance dac outputs provide a differential current output programmable over a 2 ma to 20 ma range. the ad9777 is manufactured on an advanced 0.35 micron cmos process, operates from a single-supply of 3.1 v to 3.5 v, and consumes 1.2 w of power. 1 protected by u.s. patent numbers, 5,568,145; 5,689,257; and 5,703,519. other patents pending. targeted at wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the ad9777 is ideal for wideband cdma, multicarrier cdma, multicarrier tdma, multicarrier gsm, and high performance systems employing high-order qam modulation schemes. the image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. the direct if mode helps to eliminate a costly mixer stage for a variety of communications systems. product highlights 1. the ad9777 is the 16-bit member of the ad977x pin compatible, high performance, programmable 2/4/8 interpolating txdac+ family. 2. direct if transmission is possible for 70 mhz + ifs through a novel digital mixing process. 3. f s /2, f s /4, and f s /8 digital quadrature modulation and user selectable image rejection simplify/remove cascaded saw filter stages. 4. a 2/4/8 user selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 5. user selectable twos complement/straight binary data coding. 6. user programmable channel gain control over 1 db range in 0.01 db increments. 7. user programmable channel offset control 10% over the fsr. 8. ultrahigh speed 400 msps dac conversion rate. 9. internal clock divider provides data rate clock for easy interfacing. 10. flexible clock input with single-ended or differential input, cmos, or 1 v p-p lo sine wave input capability. 11. low power: complete cmos dac operates on 1.2 w from a 3.1 v to 3.5 v single supply. the 20 ma full-scale current can be reduced for lower power operation, and several sleep functions are provided to reduce power during idle periods. 12. on-chip voltage reference: the ad9777 includes a 1.20 v temperature compensated band gap voltage reference. 13. an 80-lead thin quad flat package, exposed pad (tqfp_ep).
ad9777 rev. c | page 5 of 60 specifications dc specifications t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 1. parameter min typ max unit resolution 16 bits dc accuracy 1 integral nonlinearity 6 lsb differential nonlinearity ?6.5 3 +6.5 lsb analog output (for 1r and 2r gain setting modes) offset error ?0.025 0.01 +0.025 % of fsr gain error (with internal reference) ?1.0 +1.0 % of fsr gain matching ?1 0.1 +1 % of fsr full-scale output current 2 2 20 ma output compliance range ?1.0 +1.25 v output resistance 200 k? output capacitance 3 pf gain, offset cal dacs, monotonicity guaranteed reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 7 k? small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/c gain drift (with internal reference) 50 ppm of fsr/c reference voltage drift 50 ppm/c power supply avdd voltage range 3.1 3.3 3.5 v analog supply current (i avdd ) 4 72.5 76 ma i avdd in sleep mode 23.3 26 ma clkvdd (pll off) voltage range 3.1 3.3 3.5 v clock supply current (i clkvdd ) 4 8.5 10.0 ma clkvdd (pll on) clock supply current (i clkvdd ) 23.5 ma dvdd voltage range 3.1 3.3 3.5 v digital supply current (i dvdd ) 4 34 41 ma nominal power dissipation 4 380 410 mw p dis 5 1.75 w p dis in pwdn 6.0 mw power supply rejection ratioavdd 0.4 % of fsr/v operating range ?40 +85 c 1 measured at i outa driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external amplifier to drive any external load. 4 100 msps f dac with f out = 1 mhz, all supplies = 3.3 v, no interpolation, no modulation. 5 400 msps f dac , f data = 50 msps, f s /2 modulation, pll enabled.
ad9777 rev. c | page 6 of 60 dynamic specifications t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 0 v, i outfs = 20 ma, interpolation = 2, differential transformer-coupled output, 50 ? doubly terminated, unless otherwise noted. table 2. parameter min typ max unit dynamic performance maximum dac output update rate (f dac ) 400 msps output settling time (t st ) (to 0.025%) 11 ns output rise time (10% to 90%) 1 0.8 ns output fall time (10% to 90%) 1 0.8 ns output noise (i outfs = 20 ma) 50 pa/hz ac linearitybaseband mode spurious-free dynamic range (sfdr) to nyquist (f out = 0 dbfs) f data = 100 msps, f out = 1 mhz 71 85 dbc f data = 65 msps, f out = 1 mhz 85 dbc f data = 65 msps, f out = 15 mhz 84 dbc f data = 78 msps, f out = 1 mhz 85 dbc f data = 78 msps, f out = 15 mhz 83 dbc f data = 160 msps, f out = 1 mhz 85 dbc f data = 160 msps, f out = 15 mhz 83 dbc spurious-free dynamic range within a 1 mhz window f out = 0 dbfs, f data = 100 msps, f out = 1 mhz 73 99.1 dbc two-tone intermodulation (imd) to nyquist (f out1 = f out2 = ?6 dbfs) f data = 65 msps, f out1 = 10 mhz; f out2 = 11 mhz 85 dbc f data = 65 msps, f out1 = 20 mhz; f out2 = 21 mhz 78 dbc f data = 78 msps, f out1 = 10 mhz; f out2 = 11 mhz 85 dbc f data = 78 msps, f out1 = 20 mhz; f out2 = 21 mhz 78 dbc f data = 160 msps, f out1 = 10 mhz; f out2 = 11 mhz 85 dbc f data = 160 msps, f out1 = 20 mhz; f out2 = 21 mhz 84 dbc total harmonic distortion (thd) f data = 100 msps, f out = 1 mhz; 0 dbfs ?71 ?83 db signal-to-noise ratio (snr) f data = 78 msps, f out = 5 mhz; 0 dbfs 79 db f data = 160 msps, f out = 5 mhz; 0 dbfs 75 db adjacent channel power ratio (acpr) wcdma with 3.84 mhz bw, 5 mhz channel spacing if = baseband, f data = 76.8 msps 73 dbc if = 19.2 mhz, f data = 76.8 msps 73 dbc four-tone intermodulation 21 mhz, 22 mhz, 23 mhz, and 24 mhz at ?12 dbfs (f data = msps, missing center) 76 dbfs ac linearityif mode four-tone intermodulation at if = 200 mhz 201 mhz, 202 mhz, 203 mhz, and 204 mhz at ?12 dbfs (f data = 160 msps, f dac = 320 mhz) 72 dbfs 1 measured single-ended into 50 ? load.
ad9777 rev. c | page 7 of 60 digital specifications t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 3. parameter min typ max unit digital inputs logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf clock inputs input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v serial control bus maximum sclk frequency (f slck ) 15 mhz mimimum clock pulse width high (t pwh ) 30 ns mimimum clock pulse width low (t pwl ) 30 ns maximum clock rise/fall time 1 ms minimum data/chip select setup time (t ds ) 25 ns minimum data hold time (t dh ) 0 ns maximum data valid time (t dv ) 30 ns reset pulse width 1.5 ns inputs (sdi, sdio, sclk, csb) logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf sdio output logic 1 voltage drvdd ? 0.6 v logic 0 voltage 0.4 v logic 1 current 30 50 ma logic 0 current 30 50 ma
ad9777 r e v. c | pa ge 8 o f 6 0 digital fil t er specifications table 4. half-b and filter no. 1 (43 coe fficients) t a p c o e f f i c i e n t 1, 43 8 2, 42 0 3, 41 ?29 4, 40 0 5, 39 67 6, 38 0 7, 37 ?134 8, 36 0 9, 35 244 10, 34 0 11, 33 ?414 12, 32 0 13, 31 673 14, 30 0 15, 29 ?1,079 16, 28 0 17, 27 1,772 18, 26 0 19, 25 ?3,280 20, 24 0 21, 23 10,364 2 2 1 6 , 3 8 4 table 5. half-b and filter no. 2 (19 coe fficients) t a p c o e f f i c i e n t 1, 19 19 2, 18 0 3, 17 ?120 4, 16 0 5, 15 438 6, 14 0 7, 13 ?1,288 8, 12 0 9, 11 5,047 1 0 8 , 1 9 2 table 6. half-b and filter no. 3 (11 coe fficients) t a p c o e f f i c i e n t 1, 11 7 2, 10 0 3, 9 ?53 4, 8 0 5, 7 302 6 512 ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 20 atte nuation (dbfs ) f out (normalized to input data rate) 0.5 0 1.0 1.5 2.0 02706-003 fig u re 2. 2 int e rp ol at ing f ilt e r r e s p o n s e ? 120 ? 100 ?80 ?60 ?40 ?20 0 20 atte nuation (dbfs ) f out (normalized to input data rate) 0.5 0 1.0 1.5 2.0 02706-004 fig u re 3. 4 int e rp ol at ing f ilt e r r e s p o n s e ? 120 ? 100 ?80 ?60 ?40 ?20 0 20 atte nuation (dbfs ) f out (normalized to input data rate) 2 04 6 02706-005 8 fig u re 4. 8 int e rp ol at ing f ilt e r r e s p o n s e
ad9777 r e v. c | pa ge 9 o f 6 0 absolute maximum ra tings table 7. p a r a me t e r w i t h respec t t o m i n ma x u n i t a v dd , dvd d , c l k v dd a g nd , dg nd , c l k g nd ?0.3 +4.0 v a v dd , dvd d , c l k v dd a v dd , dvd d , c l k v dd ?4.0 +4.0 v a g nd , dg nd , c l k g nd a g nd , dg nd , c l k g nd ?0.3 +0.3 v refio , fsadj1/fsadj2 a g nd ?0.3 a v dd + 0.3 v i ou t a , i ou tb a g nd ?1.0 a v dd + 0.3 v p1b15 to p1b0, p2b15 to p2b0, rese t dgnd ?0.3 dvdd + 0.3 v d a t a clk/pll_l o ck dgnd ?0.3 dvdd + 0.3 v clk+, clk? clk g nd ?0.3 clk v dd + 0.3 v lpf clk g nd ?0.3 clk v dd + 0.3 v spi_csb , spi_cl k , spi_sdio , spi _ sd o dgnd ?0.3 dvdd + 0.3 v junc tion t e mpe r a tur e 125 c stor age t e mpera tur e ?65 +150 c l e ad t e mper a tur e (10 sec) 300 c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xi m u m r a t i n g s ma y ca us e p e r m an e n t da ma g e t o t h e de vi ce . this is a s t r e s s ra t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y ot he r c o n d it i o ns ab o v e t h o s e i n d i c a t e d i n t h e op e r a t i o n a l s e c t i o ns of t h i s s p e cif i ca tion is n o t im pli e d . e x p o sur e to a b s o lu te max i m u m r a t i n g s fo r ex te nde d p e r i o d s m a y a f fe c t de vice rel i a b i l i t y . thermal c h aracteristics ther ma l resi st anc e 8 0 - l e a d th in q u a d f l a t pa c k a g e , e x posed pa d [t q f p _ e p ] ja = 23.5c/w (w i t h t h er mal p a d s o lder ed t o pcb) esd caution esd (elec t r o sta t ic dischar g e) sensitiv e devic e . e l ec tr osta tic charges as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e with out det e c t ion. although this pr oduc t f e a tur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t dama ge may oc cur on dev i c e s sub j ec ted to high ener gy elec tr o s ta tic di scharge s . theref or e , proper esd pr ecautio n s a r e r e c o m m ended to a v oid per f or man c e degrada t ion or l o ss of func tiona l it y .
ad9777 rev. c | page 10 of 60 pin conf igura t ion and fu nction descriptions fsadj1 fsadj2 refio reset spi_csb spi_clk spi_sdio spi_sdo dgnd dvdd p2b0 (lsb) p2b1 p2b2 p2b3 p2b4 p2b5 dgnd dvdd p2b6 p2b7 02706-002 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 11 59 58 57 54 55 56 60 53 52 51 49 48 47 46 45 44 43 42 41 50 pin 1 nc = no connect 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ad9777 txdac+ top view (not to scale) av dd av dd av dd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd av dd av dd av dd i outa1 i outa 2 i outb 2 i outb1 p1b 7 p1b 6 p1b 5 p1b 4 dgnd dv dd p1b 3 p1b 2 p1b 1 p1b 0 ( l sb ) iqsel/p2b 15 ( m sb ) one p o rtclk/p 2 b1 4 p2b 1 3 p2b 1 2 dgnd dv dd p2b 1 1 p2b 1 0 p2b 9 p2b 8 clkvdd lpf clkvdd clkgnd clk+ clk? clkgnd dataclk/pll_lock dgnd dvdd p1b15 (msb) p1b14 p1b13 p1b12 p1b11 p1b10 dgnd dvdd p1b9 p1b8 figure 5. pin c o nfiguration
ad9777 rev. c | page 11 of 60 table 8. pin function description pin no. mnemonic description 1, 3 clkvdd clock supply voltage. 2 lpf pll loop filter. 4, 7 clkgnd clock supply common. 5 clk+ differential clock input. 6 clk? differential clock input. 8 dataclk/pll_lock with the pll enabled, this pin indicates the state of the pll. a read of a logic 1 indicates the pll is in the locked state. logic 0 indicates the pll has not achieved lock. this pin may also be programmed to act as either an input or outp ut (address 02h, bit 3) dataclk signal running at the input data rate. 9, 17, 25, 35, 44, 52 dgnd digital common. 10, 18, 26, 36, 43, 51 dvdd digital supply voltage. 11 to 16, 19 to 24, 27 to 30 p1b15 (msb) to p1b0 (lsb) port 1 data inputs. 31 iqsel/p2b15 (msb) in one-port mode, iqsel = 1 followed by a rising edge of the differential input clock latches the data into the i channel input register. iqs el = 0 latches the data into the q channel input register. in two-port mode, this pin becomes the port 2 msb. 32 oneportclk/p2b14 with the pll disabled and the ad9777 in one- port mode, this pin becomes a clock output that runs at twice the input data rate of the i and q channels. this allows the ad9777 to accept and demux interleaved i and q da ta to the i and q input registers. 33, 34, 37 to 42, 45 to 50 p2b13 to p2b0 (lsb) port 2 data inputs. 53 spi_sdo in the case where sdio is an input, sdo acts as an output. when sd io becomes an output, sdo enters a high-z state. this pin can also be used as an output for the data rate clock. for more information, see the two port data input mode section. 54 spi_sdio bidirectional data pin. data direction is controlled by bit 7 of register address 00h. the default setting for this bit is 0, which sets sdio as an input. 55 spi_clk data input to the spi port is registered on the ri sing edge of spi_clk. data output on the spi port is registered on the falling edge. 56 spi_csb chip select/spi data synchronization. on momentary logic high, resets spi port logic and initializes instruction cycle. 57 reset logic 1 resets all of the spi port registers, in cluding address 00h, to their default values. a software reset can also be done by writing a logic 1 to spi register 00h, bit 5. however, the software reset has no effect on the bits in address 00h. 58 refio reference output, 1.2 v nominal. 59 fsadj2 full-scale current adjust, q channel. 60 fsadj1 full-scale current adjust, i channel. 61, 63, 65, 76, 78, 80 avdd analog supply voltage. 62, 64, 66, 67, 70, 71, 74, 75, 77, 79 agnd analog common. 68, 69 i outb2 , i outa2 differential dac current outputs, q channel. 72, 73 i outb1 , i outa1 differential dac current outputs, i channel.
ad9777 rev. c | page 12 of 60 terminology adjacent channel power ratio (acpr) a ratio in dbc between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images are redundant and have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. complex modulation the process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e jt = cost + jsint) and realizing real and imaginary components on the modulator output. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. group delay number of input clocks between an impulse applied at the device input and the peak dac output current. a half-band fir filter has constant group delay over its entire frequency range. impulse response response of the device to an impulse applied to the input. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that would typically appear around f dac (output data rate) can be greatly suppressed. linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of 0 is called offset error. for i outa , 0 ma output is expected when the inputs are all 0. for i outb , 0 ma output is expected when all inputs are set to 1. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. pass band frequency band in which any input applied therein passes unattenuated to the dac output. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. stop-band rejection the amount of attenuation of a frequency outside the pass band applied to the dac, relative to a full-scale signal applied at the dac input within the pass band. temp er atu re d r i f t it is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db).
ad9777 rev. c | page 13 of 60 typical perf orm ance cha r acte ristics t = 25c, a v dd = 3.3 v , cl kvd d = 3.3 v , d v d d = 3.3 v , i ou t f s = 20 ma, i n t e r p ola t ion = 2, dif f er en tial tra n sf o r m e r - co u p led o u t p u t , 5 0 ? doubly te r m ina t e d , u n l e ss ot he r w i s e note d. ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 10 amp l itude (dbm) frequency (mhz) 0 6 5 130 02706-006 figure 6. sing le-t one spe c tru m @ f da ta = 6 5 msp s w i th f out = f da t a /3 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ?6dbfs ? 12dbfs 02706-007 figure 7. in-b and s f dr vs. f ou t @ f da t a = 6 5 ms ps 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ?6dbfs ?12dbfs 02706-008 figure 8. out-of-band sfdr vs. f ou t @ f da t a = 65 msps ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 10 amp l itude (dbm) frequency (mhz) 0 100 50 150 02706-009 figure 9. sing le-t one spe c tru m @ f da ta = 7 8 msp s w i th f out = f da t a /3 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ? 6dbfs ? 12dbfs 02706-010 f i g u r e 10 . i n -b a n d s f d r v s . f ou t @ f da t a = 78 m s ps 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ?6dbfs ?12dbfs 02706-011 figure 11. out- of-band sfdr vs. f ou t @ f da t a = 78 m s ps
ad9777 rev. c | page 14 of 60 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 10 amp l itude (dbm) frequency (mhz) 0 200 100 300 02706-012 figure 1 2 . s i ngl e -t one spectr u m @ f da t a = 160 msp s wi th f ou t = f da t a /3 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 01 0 2 0 3 0 4 0 5 0 frequency (mhz) 0dbfs ?12dbfs ? 6dbfs 02706-013 f i g u r e 13 . i n -b a n d s f d r v s . f ou t @ f da t a = 16 0 m s ps 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 01 0 2 0 3 0 4 0 5 0 frequency (mhz) 0dbfs ?6dbfs ?12dbfs 02706-014 figure 14. out- of-band sfdr vs. f ou t @ f da t a = 16 0 m s ps 50 55 60 65 70 75 imd (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ?6dbfs ? 3dbfs 02706-015 figure 15. t h ird-o r d er imd produ c ts vs. two-t o ne f ou t @ f da t a = 6 5 ms ps 50 55 60 65 70 75 imd (dbc ) 80 85 90 10 15 0 5 20 25 30 frequency (mhz) 0dbfs ?6dbfs ? 3dbfs 02706-016 figure 16. t h ird-o r d er imd produ c ts vs. two-t o ne f ou t @ f da t a = 7 8 ms ps 50 55 60 65 70 75 imd (dbc ) 80 85 90 20 30 0 1 0 4 05 06 0 frequency (mhz) 0dbfs ? 6dbfs ?3dbfs 02706-017 figure 17. t h ird-o r d er imd produ c ts vs. two-t o ne f ou t @ f da t a = 160 msp s
ad9777 rev. c | page 15 of 60 50 55 60 65 70 75 im d ( d bc) 80 85 90 20 30 0 1 0 4 05 06 0 frequency (mhz) 4 8 1 2 02706-018 figure 18. t h ird-o r d er imd produ c ts vs. two-t o ne f ou t an d int e rp ol at i o n ra te , 1 f da t a = 1 60 msp s , 2 f da ta = 1 60 m s ps, 4 f da t a = 80 m s ps , 8 f da t a = 5 0 ms ps 50 55 60 65 70 75 imd (dbc ) 80 85 90 a out (dbfs) ?15 ? 5 ?1 0 0 8 2 1 4 02706-019 figure 19. t h ird-o r d er imd produ c ts vs. two-t o ne a ou t a n d int e rp ol at i o n ra te , f da ta = 5 0 m s ps in a l l c a s e s , 1 f da c = 5 0 ms ps, 2 f da c = 10 0 msp s , 4 f da c = 20 0 msp s , 8 f da c = 40 0 m s p s 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 avdd (v) 3.2 3.1 3.3 3.4 3.5 0dbfs ?6dbfs ?12dbfs 02706-020 figure 20. sf dr vs. avdd f ou t = 10 m h z, f da c = 32 0 m s ps, f da t a = 160 msp s 50 55 60 65 70 75 imd (dbc ) 80 85 90 avdd (v) 3.2 3.1 3.3 3.4 3.5 0dbfs ?6dbfs ?3dbfs 02706-021 figure 21. t h ird-o r d er imd produ c ts vs. avdd @ f ou t = 1 0 mhz, f da c = 32 0 m s ps, f da t a = 160 msp s 50 55 60 65 70 75 s nr (db) 80 85 90 input data rate (msps) 0 100 50 150 pll off pll on 02706-022 figure 22. s n r vs. data r a te for f ou t = 5 m h z 50 55 60 65 70 75 s f dr (dbc ) 80 85 90 temperature ( c) ?50 5 0 0 100 78msps 160msps f data = 65msps 02706-023 figure 23. sf dr vs. temp er ature @ f ou t = f da ta / 11
ad9777 rev. c | page 16 of 60 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) frequency (mhz) 0 100 50 150 02706-024 figure 24. s i ngle-t one spurious pe rformanc e, f ou t = 1 0 mhz, f da t a = 1 5 0 m s ps, n o int e rpo l at ion ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbm) 01 0 2 0 3 0 4 0 5 0 frequency (mhz) 02706-025 fig u re 2 5 . t w o-t o n e im d pe rf or m a nc e , f da t a = 1 5 0 m s ps, n o int e rpo l at ion ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 100 150 0 5 0 200 250 300 frequency (mhz) 02706-026 figure 26. s i ngle-t one spurious pe rformanc e, f ou t = 1 0 mhz, f da t a = 150 msp s , inte r p ol a t i o n = 2 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbm) 0 5 10 15 20 25 30 35 40 45 frequency (mhz) 02706-027 fig u re 2 7 . t w o-t o n e im d pe rf or m a nc e , f da t a = 90 m s ps , in t e rpo l at i o n = 4 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 amp l itude (dbm) 100 150 0 5 0 200 250 300 frequency (mhz) 02706-028 figure 28. s i ngle-t one spurious pe rformanc e, f ou t = 1 0 mhz, f da t a = 8 0 m s ps, int e rpo l at io n = 4 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbm) 0 5 10 15 20 25 frequency (mhz) 02706-029 fig u re 2 9 . t w o-t o n e im d pe rf or m a nc e , f ou t = 10 m h z , f da t a = 5 0 m s ps, int e rpo l at io n = 8
ad9777 rev. c | page 17 of 60 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) frequency (mhz) 100 0 200 300 400 02706-030 figure 30. s i ngle-t one spurious pe rformanc e, f ou t = 1 0 mhz, f da t a = 5 0 m s ps, int e rpo l at io n = 8 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) frequency (mhz) 20 04 0 6 0 02706-031 8 0 fi gure 31 . ei ght-tone imd p e rforma n ce, f da t a = 16 0 m s p s , int e rp ol at i o n = 8 x
ad9777 rev. c | page 18 of 60 mode control (via spi port) table 9. mode control via spi port 1 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h sdio bidirectional 0 = input 1 = i/o lsb, msb first 0 = msb 1 = lsb software reset on logic 1 sleep mode logic 1 shuts down the dac output currents power-down mode logic 1 shuts down all digital and analog functions 1r/2r mode dac output current set by one or two external resistors 0 = 2r , 1 = 1r pll_lock indicator 01h filter interpolation rate (1, 2, 4, 8) filter interpolation rate (1, 2, 4, 8) modulation mode ( none , f s /2, f s /4, f s /8) modulation mode ( none , f s /2, f s /4, f s /8) 0 = no zero stuffing on interpolation filters , logic 1 enables zero stuffing 1 = real mix mode 0 = complex mix mode 0 = e ?jt 1 = e +jt dataclk/ pll_lock 2 select 0 = pll_lock 1 = dataclk 02h 0 = signed input data 1 = unsigned 0 = two-port mode 1 = one-port mode dataclk driver strength dataclk invert 0 = no invert 1 = invert oneportclk invert 0 = no invert 1 = invert iqsel invert 0 = no invert 1 = invert q first 0 = i first 1 = q first 03h data rate 2 clock output pll divide (prescaler) ratio pll divide (prescaler) ratio 04h 0 = pll off 2 1 = pll on 0 = automatic charge pump control 1 = programmable pll charge pump control pll charge pump control pll charge pump control 05h idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment 06h idac coarse gain adjustment idac coarse gain adjustment idac coarse gain adjustment idac coarse gain adjustment 07h idac offset adjustment bit 9 idac offset adjustment bit 8 idac offset adjustment bit 7 idac offset adjustment bit 6 idac offset adjustment bit 5 idac offset adjustment bit 4 idac offset adjustment bit 3 idac offset adjustment bit 2 08h idac i offset direction 0 = i offset on i outa 1 = i offset on i out b idac offset adjustment bit 1 idac offset adjustment bit 0 09h qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment
ad9777 rev. c | page 19 of 60 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0ah qdac coarse gain adjustment qdac coarse gain adjustment qdac coarse gain adjustment qdac coarse gain adjustment 0bh qdac offset adjustment bit 9 qdac offset adjustment bit 8 qdac offset adjustment bit 7 qdac offset adjustment bit 6 qdac offset adjustment bit 5 qdac offset adjustment bit 4 qdac offset adjustment bit 3 qdac offset adjustment bit 2 0ch qdac i offset direction 0 = i offset on i outa 1 = i offset on i outb qdac offset adjustment bit 1 qdac offset adjustment bit 0 0dh version register version register version register version register 1 default values are shown in bold. 2 for more information, see the tw o port data input mode section.
ad9777 rev. c | page 20 of 60 register description address 00h bit 7: logic 0 (default) causes the spi_sdio pin to act as an input during the data transfer (phase 2) of the communications cycle. when set to 1, spi_sdio can act as an input or output, depending on bit 7 of the instruction byte. bit 6: logic 0 (default). determines the direction (lsb/msb first) of the communications and data transfer communications cycles. refer to the msb/lsb transfers section for more details. bit 5: writing a 1 to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back 0. register address 00h bits are not cleared by this software reset. however, a high level at the reset pin forces all registers, including those in address 00h, to their default state. bit 4: sleep mode. a logic 1 to this bit shuts down the dac output currents. bit 3: power-down. logic 1 shuts down all analog and digital functions except for the spi port. bit 2: 1r/2r mode. the default (0) places the ad9777 in two resistor mode. in this mode, the i ref currents for the i and q dac references are set separately by the r set resistors on fsadj2 and fsadj1 (pins 59 and 60). in 2r mode, assuming the coarse gain setting is full scale and the fine gain setting is 0, i fullscale1 = 32 v ref /fsadj1 and i fullscale2 = 32 v ref /fsadj2. with this bit set to 1, the reference currents for both i and q dacs are controlled by a single resistor on pin 60. i fullscale in one resistor mode for both the i and q dacs is half of what it would be in 2r mode, assuming all other conditions (r set , register settings) remain unchanged. the full-scale current of each dac can still be set to 20 ma by choosing a resistor of half the value of the r set value used in 2r mode. bit 1: pll_lock indicator. when the pll is enabled, reading this bit gives the status of the pll. a logic 1 indicates the pll is locked. a logic 0 indicates an unlocked state. address 01h bit 7, bit 6: this is the filter interpolation rate according to the following table. 00 1 01 2 10 4 11 8 bit 5 and bit 4: this is the modulation mode according to the following table. 00 none 01 f s /2 10 f s /4 11 f s /8 bit 3: logic 1 enables zero stuffing mode for interpolation filters. bit 2: default (1) enables the real mix mode. the i and q data channels are individually modulated by f s /2, f s /4, or f s /8 after the interpolation filters. however, no complex modulation is done. in the complex mix mode (logic 0), the digital modulators on the i and q data channels are coupled to create a digital complex modulator. when the ad9777 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second if frequency (that is, the lo of the analog quadrature modulator external to the ad9777) according to the bit value of register 01h, bit 1. bit 1: logic 0 (default) causes the complex modulation to be of the form e ?jt , resulting in the rejection of the higher frequency image when the ad9777 is used with an external quadrature modulator. a logic 1 causes the modulation to be of the form e +jt , which causes rejection of the lower frequency image. bit 0: in two-port mode, a logic 0 (default) causes pin 8 to act as a lock indicator for the internal pll. a logic 1 in this register causes pin 8 to act as a dataclk. for more information, see the two port data input mode section. address 02h bit 7: logic 0 (default) causes data to be accepted on the inputs as twos complement binary. logic 1 causes data to be accepted as straight binary. bit 6: logic 0 (default) places the ad9777 in two-port mode. i and q data enters the ad9777 via ports 1 and 2, respectively. a logic 1 places the ad9777 in one-port mode in which interleaved i and q data is applied to port 1. see table 8 for detailed information on how to use the dataclk/pll_lock, iqsel, and oneportclk modes. bit 5: dataclk driver strength. with the internal pll disabled and this bit set to logic 0, it is recommended that dataclk be buffered. when this bit is set to logic 1, dataclk acts as a stronger driver capable of driving small capacitive loads. bit 4: logic 0 (default). a value of 1 inverts dataclk at pin 8. bit 2: logic 0 (default). a value of 1 inverts oneportclk at pin 32. bit 1: logic 0 (default) causes iqsel = 0 to direct input data to the i channel, while iqsel = 1 directs input data to the q channel. bit 0: logic 0 (default) defines iq pairing as iq, iq, while programming a logic 1 causes the pair ordering to be qi, qi
ad9777 rev. c | page 21 of 60 a d dr ess 03h bi t 7 : t h i s allo w s th e d a ta ra t e cl o c k ( d ivi d e d d o w n f r om t h e d a c c l o c k) t o be o u t p u t a t e i t h er t h e d a t a c l k/pll_l o c k p i n (p in 8) o r a t th e s p i_s d o p i n (p in 53). th e defa u l t o f 0 in th i s r e gi s t e r e n a b le s th e d a t a ra t e c l oc k a t d a t a c l k / p ll_l o c k, w h ile a 1 in t h is r e g i s t er ca us es t h e da t a ra t e c l o c k t o be o u t p u t a t s p i_s d o . f o r m o r e inf o r m a t io n, s e e t h e t w o p o r t da ta i n p u t m o d e sect i o n . bi t 1 , bi t 0 : s e t t in g t h is divi de r a t i o t o a h i g h er n u m b er a l lo ws t h e v c o in t h e p ll t o r u n a t a hig h r a t e (fo r b e s t p e r f o r ma n c e) wh ile t h e d a c in p u t a n d o u t p u t c l oc k s r u n su bs ta n t iall y s l o w e r . t h e di vi d e r ra tio i s se t a c co r d i n g t o th e f o llo w in g ta b l e . 0 0 1 0 1 2 1 0 4 1 1 8 a d dr ess 04h bi t 7 : l o g i c 0 (defa u l t ) dis a b l es t h e in t e r n al p l l. l o g i c 1 ena b les t h e pll . bi t 6 : logic 0 (defa u l t ) sets t h e c h a r g e p u m p c o n t r o l t o a u t o m a t i c . i n th i s m o d e , th e c h a r g e p u m p b i a s cu rr e n t i s co n t r o l l e d b y t h e divi der r a t i o d e f i n e d i n a d dr e s s 03h, bi ts 1 a nd 0. l o g i c 1 a l lo ws the us er to ma n u al l y def i n e t h e c h a r g e p u m p b i as c u r r en t usin g a ddr es s 04h, b i ts 2, 1, a nd 0. a d j u s t ing t h e cha r g e p u m p b i as c u r r en t al lo ws t h e us er t o o p t i mi ze t h e noi s e / s e tt l i ng p e r f or m a nc e of t h e p l l . bi t 2 , bi t 1 , bi t 0 : w i th th e c h a r g e p u m p co n t r o l se t t o m a n u al, t h es e b i ts def i n e t h e cha r g e p u m p b i as c u r r en t acco r d in g t o t h e fol l o w ing t a bl e. 0 0 0 5 0 a 0 0 1 1 0 0 a 0 1 0 2 0 0 a 0 1 1 4 0 0 a 1 1 1 8 0 0 a a d d r ess 05h, 09h b i t 7, b i t 6, b i t 5, b i t 4, b i t 3, b i t 2, b i t 1, an d b i t 0: th ese b i ts r e p r es en t an 8- b i t b i na r y n u m b er (bi t 7 ms b) t h a t def i n e s t h e f i n e ga in ad j u s t m e n t o f t h e i (0 5h) a nd q (09h) d a c acco r d ing to e q u a t i on 1 . a d d r ess 06h, 0ah bi t 3 , bi t 2 , bi t 1 , a n d bi t 0 : thes e b i ts r e p r es e n t a 4 - b i t b i na r y n u m b e r (b i t 3 ms b) th a t de f i n e s th e coa r se ga in a d j u s t m e n t o f th e i (06 h ) a nd q (0ah) d a cs acco r d in g t o e q ua tio n 1. a d d r ess 07h, 0b h b i t 7, b i t 6, b i t 5, b i t 4, b i t 3, b i t 2, b i t 1, an d b i t 0: th ese b i ts a r e us ed in co n j un c t ion wi th a ddr es s 08 h, 0ch, b i ts 1, 0. a d d r ess 08h, 0c h b i t 1 an d b i t 0: the 10 b i ts f r o m t h es e tw o addr es s p a irs (07h, 08h an d 0bh, 0 c h) r e p r es en t a 10-b i t b i na r y n u m b er tha t def i n e s t h e o f fs et ad j u s t m e n t o f t h e i and q d a cs acco r d i n g t o e q ua tion 1. (07 h , 0b hCb i t 7 m s b/08h, 0c hCbi t 0 ls b). a d d r ess 08h, 0c h bi t 7 : this b i t det e r m i n es t h e di r e c t io n o f t h e o f fs et o f t h e i (08h) a nd q (0ch) d a cs. a l o gic 0 a p p l ies a p o si ti v e o f fset cu rr e n t t o i ou t a , w h i l e a l o g i c 1 a p plies a p o si t i ve o f fs et c u r r en t to i ou t b . th e mag n i t u d e o f t h e of fs et c u r r en t is def i n e d b y t h e b i ts in a d dr es s e s 07h, 0b h, 08 h, 0ch acco r d in g t o e q ua tion 1. e q ua tion 1 sh o w s i ou t a and i ou t b as a f u n c t i on o f fi n e ga i n , coa r se ga in , a n d o f fset ad j u s t m e n t w h en us in g 2r m o d e . i n 1r m o d e , t h e c u rr en t i re f is cre a te d b y a sing l e fs a d j r e sist o r (p in 60). th is c u rr en t i s d i vid e d eq uall y in t o each c h a n n e l so t h a t a s c a l i n g f a c t or of o n e - h a l f m u st b e a d d e d to t h e s e e q u a t i on s f o r full- scale cu rr en t s f o r bo th d a cs a n d th e o f fset. ) ( 1024 4 ) ( 2 1 2 24 1024 256 32 3 16 1 8 6 ) ( 2 24 1024 256 32 3 16 1 8 6 16 16 16 a offset i i a data fine i coarse i i a data fine i coarse i i ref offset ref ref outb ref ref outa ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = ( 1 )
ad9777 rev. c | page 22 of 60 functional description the ad9777 d u al in t e r p ola t in g d a c co n s ists o f tw o da t a cha nnels t h a t can b e o p er a t e d i n d e p e nden t ly o r co u p le d to fo r m a c o m p l e x mo du l a tor i n an i m a g e re j e c t t r ans m i t arch ite c t u re. e a c h c h a n ne l inc l udes thr e e fi r f i l t ers, mak i ng th e ad9777 ca p a b l e o f 2, 4 , o r 8 in ter p ola t ion. h i g h sp e e d i n p u t and o u t p ut da t a r a te s ca n b e achie v e d w i t h in t h e fol l o w in g li m i ta ti o n s. i n te r p o l at i o n r a te (msps) input da ta r a te (msps) d a c s a mple r a t e (msps) 1 1 6 0 1 6 0 2 1 6 0 3 2 0 4 1 0 0 4 0 0 8 5 0 4 0 0 b o t h d a t a chan nels co n t ain a d i g i t a l mo d u la t o r ca p a b l e o f m i xi n g th e d a t a s t r e a m w i th a n l o o f f da c /2, f dac /4, o r f dac /8, w h er e f dac i s th e o u t p u t d a ta ra t e o f th e d a c . a z e r o st uf f i n g fe a t ur e is a l s o i n cl ude d and can b e us e d to i m p r o v e p a ss-b and f l a t n e s s fo r sig n als bein g a t t e n u a t e d b y t h e s i n(x)/x c h a r ac t e r i s t ic o f th e d a c o u t p u t . th e sp ee d o f th e ad9777, co m b in e d wi t h i t s dig i tal m o d u la tion c a p a b i li ty , ena b les dir e c t if co n v ersio n ar c h i t ec t u r e s a t 7 0 mh z and hig h er . the dig i t a l m o d u la t o rs o n the ad9777 ca n be c o u p led t o f o r m a co m p lex m o d u la t o r . b y usin g this f e a t ur e wi t h a n ext e r n al a n alog q u adra t u r e m o d u l a t o r , s u c h as t h e ana l og devices ad8345, a n ima g e r e jec t io n a r c h i t ec t u r e can b e ena b le d . t o o p ti mi ze th e ima g e r e jecti o n ca pa b i l i t y , a s w e ll a s l o f eed - thr o ug h in this a r c h i t ec t u r e , t h e ad9777 o f f e rs p r og ra mma b l e (via t h e s p i p o r t ) ga in an d o f fs et ad j u s t f o r eac h d a c. als o in c l uded on t h e ad9777 ar e a p h as e-lo ck e d lo o p (p ll) clo c k m u l t i p lier a nd a 1.20 v b a nd ga p vol t a g e r e fer e n c e. w i t h t h e p ll ena b le d, a clo c k a p plie d t o t h e clk+ /c lk? i n p u ts is f r e q u e nc y m u lt ipl i e d i n te r n a l ly an d ge ne r a te s a l l ne c e ss ar y in t e r n a l sy n c hro n iz a t io n clo c k s . e a ch 16- b i t d a c p r o v i d es t w o c o m p l e m e n t a r y cu rr e n t o u t p u t s wh os e full - s cale cu rr e n t s c a n be det e r m in ed ei t h er f r o m a sing le ext e r n al r e sis t o r o r inde- p e nde n t ly f r o m tw o s e p a r a te r e sisto r s (s e e t h e 1 r /2r m o de s e c t io n). th e ad9777 f e a t ur es a lo w ji t t er , dif f er en tial c l o c k in p u t t h a t p r o v i d es exce l l en t n o is e r e je c t ion w h i l e accep t in g a sin e o r s q ua r e wa v e in p u t. s e p a r a t e v o l t a g e s u p p l y in p u ts a r e p r o v ided f o r eac h f u n c tio n al b l o c k t o en sur e o p tim u m n o is e an d d i s t or t i on p e r f or m a nc e. sle e p a nd p o w e r - do wn mo des ca n b e us e d to tur n o f f t h e d a c o u t p ut c u r r en t ( s le ep) o r t h e e n t i r e dig i t a l and ana l o g s e c t io n s (p o w er -do w n) o f th e c h i p . a s p i-co m p l i an t s e r i al p o r t is us ed t o p r og ra m th e ma n y f e a t ur es o f th e ad9777. n o t e t h a t in p o w e r - do wn mo de, t h e s p i p o r t is t h e o n ly s e c t io n o f t h e chi p st i l l ac t i v e . sdo (pin 53) sdio (pin 54) spi_clk (pin 55) csb (pin 56) ad9777 spi port interface 02706-032 figure 3 2 . s p i po rt i n terfac e serial interface for register contr o l the ad9777 s e r i al p o r t is a f l exi b le , sy n c hr ono u s s e r i al co mm un ic a t io ns p o r t t h a t a l lo w s e a sy in t e r f a c e t o ma n y ind u s t r y -s tandar d micr o c o n tr ol lers a n d micr o p r o ces s o r s. th e s e r i al i / o is com p a t i b le wi th m o s t sy n c hr on ous tra n sfer f o r m a t s, inc l udin g bo t h t h e m o t o r o la s p i? an d i n te l? ss r p r o t o c ols. th e in t e r f ac e al lo ws r e ad/wr i t e acce ss t o al l r e g i s t ers tha t co nf igur e t h e ad9777. s i ng le- o r m u l t i p l e -b yte tra n sf ers are supp or te d a s wel l a s m s b f i r s t or l s b f i r s t t r ans f e r for m a t s . the ad9777 s s e r i al in ter f ace p o r t ca n b e co nf igur ed as a sing le p i n i/o (s d i o) o r tw o unidir e c t i o n al p i ns fo r i / o (s d i o/s d o ) . general operation of the serial interface ther e a r e tw o phas es t o a co mm uni c a t io n c y cle w i t h t h e ad9777. p h as e 1 is th e in s t r u c t io n c y c l e , whic h is th e wr i t in g o f a n ins t r u c t io n b y t e in t o the ad9777 co in c i den t wi th t h e f i rs t eig h t scl k r i sin g e d g e s. the i n s t r u c t io n b y t e p r o v ide s t h e ad9777 s e r i al p o r t co n t r o l l er wi th inf o r m a t ion r e ga r d in g t h e da ta tra n sf e r c y c l e , wh i c h i s p h a s e 2 o f th e co mm un ica t i o n c y cle . th e p h as e 1 in s t r u c t io n b y t e def i n e s w h et her t h e u p com- in g da ta tra n sf er is r e ad o r wr i t e , t h e n u m b er of b y t e s in t h e da t a t r a n sfer , and t h e s t a r t i n g r e g i s t er addr es s fo r t h e f i rs t b y t e o f th e da ta tra n sf e r . t h e f i r s t ei g h t sc lk ri si n g ed g e s o f ea c h co mm unic a t io n c y cle a r e us e d t o wr i t e t h e i n s t r u c t io n b y t e in t o th e ad9777. a l o g i c 1 o n t h e s p i_cs b p i n, f o l l o w ed b y a log i c lo w , r e s e ts t h e s p i p o r t t i min g t o t h e ini t ial s t a t e o f t h e ins t r u c t io n c y cle . this is t r ue r e ga r d les s o f t h e p r e s en t s t a t e o f t h e in t e r n al r e g i s t ers o r t h e o t h e r sig n a l le ve ls p r es en t a t t h e in pu ts t o t h e s p i p o r t . i f t h e s p i p o r t is in t h e middle o f a n in s t r u c t io n c y c l e o r a da ta tra n sf er c y c l e , n o n e o f th e p r e s e n t da t a i s w r i t t e n . the r e ma inin g sclk e d g e s a r e fo r p h as e 2 o f t h e co mm un ic a t io n c y cle . phas e 2 is t h e ac t u a l d a t a t r a n sfer betw een t h e ad9777 a nd t h e sys t em co n t r o l l e r . p h as e 2 o f t h e co mm un ic a t io n c y cle is a t r a n sf er o f o n e t o fo ur d a t a b y t e s, as det e r m i n e d b y t h e in st r u c t io n b y t e . n o r m a l ly , u s in g o n e m u l t i- b y t e t r a n sfer is t h e p r efer r e d m e t h o d . h o w e v e r , sin g le b y t e da t a tra n sfers a r e us e f u l t o r e d u ce c p u o v erh e ad w h e n r e g i s t er ac c e ss re qu ire s one b y te on ly . r e g i ste r s chang e im me d i a t ely up on w r it i n g to t h e l a st bit of e a ch t r ans f e r b y t e .
ad9777 rev. c | page 23 of 60 instruction byte the instruction byte contains the information shown below. n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes r/w bit 7 of the instruction byte determines whether a read or a write data transfer occurs after the instruction byte write. logic 1 indicates read operation. logic 0 indicates a write operation. n1, n0 bit 6 and bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the following table. msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 a4, a3, a2, a1, a0 bit 4, bit 3, bit 2, bit 1, and bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9777. serial interface port pin descriptions spi_clk (pin 55)serial clock the serial clock pin is used to synchronize data to and from the ad9777 and to run the internal state machines. spi_clk maximum frequency is 15 mhz. all data input to the ad9777 is registered on the rising edge of spi_clk. all data is driven out of the ad9777 on the falling edge of sclk. spi_csb (pin 56)chip select active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the spi_sdo and spi_sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. spi_sdio (pin 54)serial data i/o data is always written into the ad9777 on this pin. however, this pin can be used as a bidirectional data line. bit 7 of register address 00h controls the configuration of this pin. the default is logic 0, which configures the spi_sdio pin as unidirectional. spi_sdo (pin 53)serial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9777 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the ad9777 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the lsb first bit in register 0. the default is msb first. when this bit is set active high, the ad9777 serial port is in lsb first format. in lsb first mode, the instruction byte and data bytes must be written from lsb to msb. in lsb first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. when this bit is set default low, the ad9777 serial port is in msb first format. in msb first mode, the instruction byte and data bytes must be written from msb to lsb. in msb first mode, the serial port internal byte address generator decre- ments for each byte of the multibyte communication cycle. when incrementing from 1fh, the address generator changes to 00h. when decrementing from 00h, the address generator changes to 1fh.
ad9777 rev. c | page 24 of 60 instruction cycle data transfer cycle cs s cl k sdio sdo r/w i4 i3 i2 i1 i0 d7 n d6 n d7 n d6 n d2 0 d1 0 d0 0 d2 0 d1 0 d0 0 i6 (n) i5 (n) 02706-033 figure 3 3 . s e r i a l r e gis t er inte rfac e t i m i ng msb f i rs t cs sclk sdio sdo instruction cycle data transfer cycle i0 i1 i2 i3 i4 i5 (n) i6 (n) r/w d0 0 d1 0 d2 0 d6 n d7 n d0 0 d1 0 d2 0 d6 n d7 n 02706-034 figure 3 4 . s e r i a l r e gis t er inte rfac e t i m i ng lsb f i rs t t cs sclk sdio t ds t sclk t pwh t ds t dh t pwl instruction bit 7 instruction bit 6 02706-035 fi gur e 35 . tim i ng di a g r a m f o r re g i ste r w r i t e to ad97 77 cs sclk sdio sdo data bit n t dv data bit n?1 02706-036 figure 3 6 . t i ming diag ra m f o r r e g i s t er r e ad fr om a d 9 7 77
ad9777 rev. c | page 25 of 60 notes on serial port operation the ad9777 s e r i al p o r t co nf ig ura t io n b i ts r e side in b i t 6 and bi t 7 o f reg i st er a ddr ess 00 h. i t is im p o r t a n t t o n o te t h a t t h e co nf igura t io n cha n ges im m e d i a t e l y up o n wr i t i n g t o t h e la st b i t o f t h e r e g i st er . f o r m u l t ib yt e t r an sfers, wr i t i n g to t h is r e g i s t er ma y o c c u r d u r i n g t h e mi dd le of t h e co m m u n ic a t io n c y cle. c a re m u st b e t a k e n to co m p en s a te fo r t h is ne w co nf igur a t io n fo r t h e r e ma ini n g b y t e s o f t h e c u r r en t c o mm uni c a t io n c y cle . the s a m e co n s i d era t io n s a p pl y t o s e t t in g t h e r e s e t b i t in reg i st er a d dr ess 00h. al l other r e g i s t ers a r e s e t t o th e i r def a u l t va l u es, b u t t h e s o f t wa r e r e s e t do es n o t a f fe c t t h e b i ts in r e g i st er a ddr ess 00 h. i t is r e co mm e nde d t o us e onl y sin g le b y t e tra n sfers wh en cha n g i n g s e r i a l p o r t co nf igura t i o n s o r ini t ia t i n g a s o f t wa r e re s e t . a wr i t e t o b i t 1, b i t 2, an d b i t 3 o f a ddr es s 00h wi th t h e s a m e log i c lev e l s as f o r b i t 7, b i t 6, and b i t 5 (b i t p a t t er n: x y 1001yx b i na r y ) al lo ws t h e us er t o r e p r og ra m a los t s e r i al p o r t co nf igu- r a t i o n and to r e s e t t h e r e g i sters to t h e i r def a u l t va l u es. a s e cond wr i t e to a d dr ess 00h w i t h r e s e t b i t lo w an d s e r i a l p o r t co nf igu- ra tio n as sp ecif ied abo v e (xy) r e p r og ra m s th e osc in mu l t i p l i e r s e t t i n g . a c h a n g e d f sy s c l k f r e q u e nc y i s st abl e af t e r a max i m u m o f 20 0 f mc l k c y c l es (eq u als wak e -u p t i me). dac o p era t io n the d u al 16 -b i t d a c o u t p u t o f t h e ad9777, alon g wi t h t h e r e f e re n c e c i rc u i t r y , g a i n , a n d of f s e t re g i s t e r s , i s s h ow n i n f i g u r e 37 a nd f i gur e 3 8 . n o te t h a t an ex ter n a l r e fer e nce ca n b e us e d b y sim p l y o v er dr iv in g t h e in t e r n al r e fer e n c e w i t h t h e ext e r n al re fe re nc e. r e fe r r i ng to t h e t r ans f e r f u nc t i ons i n e q u a t i o n 1 , a re f e re nc e c u r r e n t i s s e t b y t h e i n te r n a l 1 . 2 v re f e re nc e, t h e ext e r n al r set r e sis t o r , a nd t h e va l u es in t h e co a r s e ga in r e g i st er . the f i n e ga in d a c s u b t rac t s a smal l a m oun t f r o m this and t h e r e s u l t is in p u t to id a c an d qd a c , wher e i t is s c ale d b y a n a m o u n t eq ual to 1024/24. f i gu r e 39 a n d f i gure 40 sh o w t h e s c a l in g ef fe c t o f t h e co a r s e an d f i ne a d j u st d a c s . id a c and qd a c a r e pmos c u r r en t s o urce a r ra ys, s e g m en t e d i n a 5-4 - 7 co nf igura t io n. the f i v e ms b c o n t r o l a n a r ra y o f 31 c u r r en t s o ur ces. th e n e xt f o ur b i ts co n s is t o f 15 c u r r en t s o ur ces w h os e val u es a r e al l e q ual t o 1/16 o f an ms b c u r r en t s o ur ce . th e 7 ls bs a r e b i na r y w e ig h t e d f r ac t i on s o f t h e middl e b i ts c u r r en t s o ur ces. al l c u r r en t s o ur ces a r e swi t ch e d t o ei t h er i ou t a or i outb , dep e ndi n g o n t h e in pu t co de. th e f i n e ad j u s t m e n t o f th e ga in o f eac h c h a n n e l all o ws f o r im - pr ove d b a l a n c e of q a m m o du l a t e d s i g n a l s , r e su lt i n g i n i m pr o v e d mo d u l a t i on a c c u r a c y and i m age r e j e c t i o n . i n t h e i n t e r f a c i n g w i t h th e ad8345 q u adra t u r e m o d u l a t o r s e c t i o n , t h e p e r f o r m a n c e da t a sh o w s to w h a t deg r e e ima g e r e j e c t io n ca n b e im p r o v e d w h en th e ad9777 is u s ed wi th a n ad8345 q u ad ra t u r e m o d u la t o r f r o m anal og device s, i n c. the o f fs et co n t rol def i n e s a sma l l c u r r en t t h a t c a n b e ad de d to i ou t a or i ou tb (no t bo t h ) o n t h e id a c an d qd a c . th e s e lec t ion of w h i c h i ou t t h is o f fs et c u r r en t is dir e c t e d t o w a r d is p r og ra m- ma b l e via reg i st er 08h, b i t 7 (i d a c) an d reg i s t er 0ch, b i t 7 (qd a c). f i gur e 42 sh o w s t h e s c ale o f t h e o f fs et c u r r en t t h a t can b e a d d e d to o n e of t h e c o m p l e me n t ar y output s on t h e i d a c a nd qd a c . of fs et co n t r o l ca n b e us e d fo r su p p r essio n o f lo l e a k a ge re su lt i n g f r om mo d u l a t i on of d c s i g n a l c o m p o n e n t s . i f th e ad9777 is dc-co u p l ed t o an ext e r n al mo d u l a t o r , this f e a t ur e ca n be us e d t o c a n c e l t h e o u t p u t o f fs et o n th e ad9777 as w e l l as t h e in p u t o f fs et o n t h e m o d u l a to r . f i gur e 42 sho w s a typ i c a l exa m ple o f t h e ef fe c t t h a t t h e of fs et co n t r o l has o n l o s u ppre s s i on . fine gain dac fine gain dac coarse gain dac coarse gain dac offset dac offset dac gain control registers offset control registers gain control registers offset control registers 1.2vref idac qdac refio 0.1 f fsadj1 rset1 i outa1 i outa2 i outb1 i outb2 rset2 fsadj2 02706- 037 figure 3 7 . da c o u tputs, r e feren c e cu r r ent s c a ling, and g a in /offset a d just 8 4 a 7k ? 0.7v refio avdd 02706-038 figure 3 8 . int e rn al r e feren ce e q u i v a l e nt cir c uit 2r m o de 1r m o d e 0 5 10 15 20 25 coars e re fe re nce curre nt (ma) coarse gain register code (assuming rset1, rset2 = 1.9k ? ) 5 01 0 1 5 02706-039 2 0 figure 3 9 . c o a r se g a in e ffect on i fullsca le
ad9777 rev. c | page 26 of 60 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 fine re fe re nce curre nt (ma) 0 1r mode 2r mode fine gain register code (assuming rset1, rset2 = 1.9k ? ) 200 400 600 800 1000 02706-040 figure 4 0 . f i ne ga i n e ffect on i fullsca le i n f i gur e 42, t h e nega t i ve s c ale r e p r es en ts an o f fs et adde d t o i ou t b , w h i l e t h e p o si t i v e s c ale r e p r es en ts an o f fs et adde d t o i ou t a o f t h e r e s p e c t i ve d a c. of fs et r e g i s t er 1 co r r es p o n d s t o id a c , while of fs et reg i s t er 2 co r r es p o n d s t o q d a c . f i gur e 42 r e p r es en ts t h e ad9777 syn t h e sizing a com p lex sig n al tha t is th en dc -co u p l e d t o a n ad8345 q u adra t u r e m o d u l a t o r wi t h a n l o o f 800 mh z. the dc co u p l i ng al lo ws t h e in p u t o f fs et o f th e ad8345 t o be c a lib r a t e d o u t as w e l l . the l o s u p p r es sio n a t t h e ad8345 o u t p u t was o p timize d f i rs t b y ad j u s t in g of fs et reg i st er 1 in t h e ad9777. w h en a n o p t i mal p o in t was f o und (r o u g h l y c o de 54), this co de was he ld in of fs et reg i s t er 1, an d of fs et reg i st er 2 was ad j u st e d . the r e s u l t ing l o s u p p r es sio n i s 70 dbf s . t h e s e a r e ty p i ca l n u m b ers, and t h e sp e c if ic co de fo r opt i m i z a t i on v a r i e s f r om p a r t to p a r t . 0 1 2 3 4 5 offs e t curre nt (ma) 0 coarse gain register code (assuming rset1, rset2 = 1.9k ? ) 2r mode 1r mode 0 200 400 600 800 1000 02706-041 figure 4 1 . da c o u tput offs et current ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 lo su ppr ession ( d b f s) ?2 0 ?1 0 0 0 ?256 ? 768 ?512 ? 1024 2 5 6 5 1 2 7 6 8 1 0 2 4 dac1, dac2 (offset register codes) offset register 1 adjusted offset register 2 adjusted, with offset register 1 set to optimized value 02706-042 figure 4 2 . offset a d just contr o l, e ffect on lo s u ppressi o n 1r/2r mode i n 2 r mo d e , t h e re f e re nc e c u r r e n t f o r e a ch ch an n e l i s s e t inde p e n d e n t l y b y t h e f s a d j r e sisto r o n t h a t ch a nnel. t h e ad9777 can be p r og ra mm ed t o der i v e i t s r e f e r e n c e c u r r en t f r om a s i ng l e re s i stor on pi n 6 0 b y putt i n g t h e p a r t i n to 1 r m o d e . t h e tra n sf e r fun c ti o n s in eq ua ti o n 1 a r e v a lid f o r 2r m o de. i n 1r mo de, t h e c u r r en t de velo p e d i n t h e sin g le f s a d j re s i stor is spl i t e q u a l l y b e t w e e n t h e two chan nel s . t h e re su l t is tha t in 1r m o de, a s c ale fac t o r of 1/2 m u s t be a p p l ied t o t h e fo r m u l as in e q u a t i o n 1. th e f u l l - s c al e d a c c u r r en t in 1r m o de ca n s t il l b e s e t to as hig h as 20 ma b y usin g t h e in t e r n al 1.2 v r e f e r e n c e an d a 950 ? r e sis t o r in s t ead o f t h e 1. 9 k? r e sis t o r typ i c a l l y us e d i n 2r m o de . clock i n pu t co nfigur atio n the clo c k in pu t s t o t h e ad977 7 ca n b e dr i v en dif f er en t i al l y o r sin g le-e nde d . th e in t e r n al c l o c k cir c ui tr y has su p p l y a n d g r ou nd ( c l k v d d , c l k g n d ) s e p a r a te f r om t h e ot he r s u ppl i e s o n t h e chi p t o mini mi ze ji t t er f r o m in t e r n al no is e s o ur ces. f i gur e 43 sh o w s th e ad9777 dr iv en f r o m a sin g l e -en d e d c l o c k s o ur ce . th e cl k+/cl k ? p i n s fo r m a dif f er en t i al in pu t (clkin) s o t h a t t h e st a t ic a l ly t e r m ina t e d in put m u st b e dc- b i as e d t o t h e mi dswi n g v o l t a g e l e v e l o f t h e clo c k dr i v en in pu t. ad9777 r series clk+ clk ? 0.1 f clkvdd clkgnd v threshold 02706-043 figure 43. s i ngle-ended clock dr iving clock inputs
ad9777 rev. c | page 27 of 60 a co nf igur a t ion fo r dif f er en t i a l ly dr i v i n g t h e cl o c k i n p u ts is g i v e n in f i gur e 44. d c -b lo c k ing ca p a ci t o rs can be us e d t o co u p le a clo c k dr i v er o u t p u t w h os e v o l t a g e s w i n gs exce e d clkvdd o r clk g nd . i f t h e dr i v er v o l t a g e s w i n gs a r e wi t h i n t h e s u p p l y ra n g e o f t h e ad977 7, t h e dc-b l o cki n g ca p a c i t o rs and b i as r e sis t o r s a r e n o t n e ces s a r y . ad9777 clk+ 0.1 f 0.1 f 0.1 f 1k ? 1k ? 1k ? 1k ? ecl/pecl clk ? clkvdd clkgnd 02706-044 fig u re 4 4 . d i f f e r e nt ia l cl ock dr iv ing c l ock input s a tra n sfo r m e r , suc h as t h e t1-1 t f r o m mini-cir c u i t s, can als o b e us e d t o con v er t a sin g le- e n d e d clo c k t o dif f er en t i al . this m e tho d is us e d o n t h e ad9777 eval ua t i o n bo a r d s o tha t a n ext e r n al sin e wa v e wi t h n o dc o f fs et can b e us ed as a dif f er en t i al cl o c k. pecl/ec l dr i vers r e q u ir e va r y in g t e r m ina t io n n e tw o r ks, t h e det a i l s o f w h ich a r e lef t o u t o f f i gur e 43 a nd f i g u r e 44 b u t c a n b e fo u n d in a p plica t io n n o t e s such as a n d802 0/d f r o m on s e micond uc to r . th e s e n e tw o r k s dep e nd o n t h e assu m e d t r a n smissio n l i ne im p e dan c e and p o w e r su p p ly vol t a g e o f t h e c l o c k dr i v er . o p tim u m p e r f o r ma n c e o f t h e ad9777 is ac hiev e d when t h e dr i v er is p l aced v e r y c l os e t o the ad9 777 c l o c k in p u ts, th er e b y nega ting a n y tra n smis sio n lin e ef fe c t s suc h as r e f l e c - ti o n s d u e t o m i sm a t ch . the qua l i t y o f t h e clo c k an d d a t a i n p u t s i g n a l s is im p o r t an t i n achie v i n g o p t i m u m p e r f o r ma n c e . th e ext e r n a l clo c k dr i v er cir c ui tr y s h o u l d p r o v ide t h e ad9777 wi th a lo w ji t t er c l o c k in p u t t h a t m e et s t h e min i m u m / max i m u m lo g i c le vels w h i l e p r o v idin g fas t e d g e s. al t h o u g h fas t c l o c k e d g e s he l p minimize a n y j i t t e r t h a t m a nifests i t s e lf as phas e n o is e o n a r e co n s t r uc t e d wa v e f o r m , t h e hig h ga in bandwid th p r o d uc t o f t h e ad9777 s c l o c k in p u t com p a r a t o r ca n t o lera t e dif f er en tial sin e wa v e in p u ts as lo w as 0.5 v p-p w i t h min i m a l deg r a d a t io n of t h e o u t p ut noi s e f l o o r . programmable pll clki n can f u nc t i o n ei t h er as an i n p u t d a t a r a te clo c k (pll ena b le d) o r as a d a c da t a r a te clo c k (pll dis a b l e d ) acco r d in g t o t h e s t a t e o f a ddr es s 02 h, bi t 7 in t h e sp i p o r t r e g i s t er . th e in t e r n al o p era t i o n o f t h e ad97 77 clo c k cir c ui t r y in t h es e t w o m o des is i l l u st r a te d in f i gur e 4 5 a nd f i gur e 46. the p ll clo c k m u l t i p li er a nd dis t r i b u t i o n c i r c u i t r y p r o d uce t h e n e cess a r y in t e r n al syn c hr o n ize d 1, 2, 4, a nd 8 c l o c ks f o r t h e r i si n g e d ge t r ig ger e d la t c h e s , in ter p ola t ion f i l t ers, m o d u l a t o rs, and d a c s . this c i r c ui t r y co n s ists o f a phas e d e t e c t o r , c h a r g e p u m p , v o l t a g e c o n t r o ll ed osc i lla t o r (v co ), p r es ca ler , clo c k dist r i b u t i o n , and s p i p o r t co n t rol. the cha r ge p u m p , v c o , dif f er en t i al clo c k i n p u t b u f f er , phas e de t e c t o r , p r es ca ler , an d cl o c k di st r i b u t i on a r e a l l p o w e r e d f r o m clkvd d . p ll lo c k s t a t us is indic a t e d b y the l o g i c sig n al a t t h e p ll_l o c k p i n, as w e l l as b y t h e s t a t us o f b i t 1, reg i st er 00h. t o en s u r e o p t i m u m phas e n o i s e p e r f o r ma n c e f r o m t h e p l l clo c k m u l t i p lier a nd dist r i b u t i on, cl kvdd sho u ld o r ig ina t e f r o m a cle a n a n a l o g su p p ly . t a ble 10 def i n e s t h e mini m u m in p u t da t a r a te s versus t h e in ter p ola t ion an d pl l divi der s e t t ing. i f t h e in p u t da t a r a te dro p s b e lo w t h e d e f i n e d mi ni m u m un der t h e s e condi t i on s, v c o phas e n o is e ca n i n cr e a s e sig n if ican t l y . the v c o sp e e d is a f u n c t i o n o f t h e in pu t da t a ra t e , t h e in t e r p ola t ion ra te , an d t h e v c o p r es ca ler , acco r d in g t o th e f o llo w i n g fun c ti o n : () () = ad9777 pllvdd input data latches pll_lock 1 = lock 0 = no lock spi port lpf clk+ clk ? interpolation filters, modulators, and dacs clock distribution circuitry interpolation rate control internal spi control registers modulation rate control pll control (pll on) pll divider (prescaler) control prescaler vco phase detector charge pump 2 1 48 02706- 045 fi gur e 45 . p ll and cl oc k ci rcui try wi th p ll ena b led
ad9777 rev. c | page 28 of 60 ad9777 input data latches pll_lock 1 = lock 0 = no lock spi port clk+ clk? interpolation filters, modulators, and dacs clock distribution circuitry interpolation rate control internal spi control registers modulation rate control pll control (pll on) pll divider (prescaler) control prescaler vco phase detector charge pump 2 1 48 02706-046 figure 46. pll and clock ci rcuitry with pll disabled in addition, if the zero stuffing option is enabled, the vco doubles its speed again. phase noise can be slightly higher with the pll enabled. figure 47 illustrates typical phase noise performance of the ad9777 with 2 interpolation and various input data rates. the signal synthesized for the phase noise measurement was a single carrier at a frequency of f data /4. the repetitive nature of this signal eliminates quantization noise and distortion spurs as a factor in the measure- ment. although the curves blend in figure 47, the different conditions are given for clarity in the table preceding figure 47. figure 47 also contains a table detailing pll divider settings vs. interpolation rate and maximum and minimum f data rates. note that maximum f data rates of 160 msps are due to the maximum input data rate of the ad9777. however, maximum rates of less than 160 msps and all minimum f data rates are due to maximum and mini- mum speeds of the internal pll vco. figure 48 shows typical performance of the pll lock signal (pin 8 or pin 53) when the pll is in the process of locking. table 10. pll optimization interpolation rate divider setting minimum f data maximum f data 1 1 32 160 1 2 16 160 1 4 8 112 1 8 4 56 2 1 24 160 2 2 12 112 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14 8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7 table 11. required pll prescaler ration vs. f data f data (msps) pll prescaler ratio 125 disabled 125 enabled div 1 100 enabled div 2 75 enabled div 2 50 enabled div 4 ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 phase noise (dbfs) 012345 frequency offset (mhz) 02706-047 figure 47. phase noise performance 02706-048 figure 48. pll_lock output signal (p in 8) in the process of locking (typical lock time) it is important to note that the resistor/capacitor needed for the pll loop filter is internal on the ad9777. this suffices unless the input data rate is below 10 mhz, in which case an external series rc is required between the lpf and clkvdd pins.
ad9777 rev. c | page 29 of 60 power diss ipatio n the ad9777 has thr e e v o l t a g e su p p lies: d v d d , a v d d , a nd clkvd d . f i gu r e 49, f i gur e 50, a nd f i gur e 51 sh o w t h e c u r r en t r e q u ir ed f r o m e a c h o f th es e su p p l ies w h en eac h is s e t t o t h e 3.3 v n o minal sp ecif ied f o r the ad9777. p o w e r dis s i p a t io n (p d ) ca n e a si l y b e ext r ac t e d b y m u l t i p l y in g t h e g i v e n c u r v es b y 3.3. a s f i gur e 49 sho w s, i dv d d is v e r y dep e n d e n t on t h e in p u t d a t a ra t e , t h e i n t e r p o l a t i o n ra t e , a n d th e a c ti va ti o n o f th e i n t e rn al dig i t a l m o d u l a to r . i dv d d , ho w e v e r , i s rel a t i vely i n s e ns it ive to t h e m o d u l a tion ra t e b y i t s e lf . i n f i g u r e 50, i av d d sho w s t h e s a me typ e o f s e n s i t iv i t y t o da t a , i n t e r p ola t ion ra te , and t h e m o d u l a to r f u n c tion b u t t o a m u ch les s er deg r ee (<10%). i n f i gur e 51, i clkv d d va r i es o v er a wi de ra n g e yet is r e s p o n si b l e fo r o n l y a smal l p e r c en t a ge o f th e o v eral l ad9777 s u p p l y c u r r en t re qu i r e m e n t . 8 4 2 1 0 50 100 150 200 250 i dv dd (ma) 300 350 400 f data (mhz) 50 0 100 150 200 8 , (mod. on) 4 , (mod. on) 2 , (mod. on) 02706-049 figure 49. i dvdd vs. f da t a vs. interpola t i o n ra te, p ll di sa b l ed 8 , (mod. on) 8 4 2 1 72.0 72.5 73.0 73.5 74.0 74.5 i av dd (ma) 75.0 75.5 76.0 f data (mhz) 50 0 100 150 200 4 , (mod. on) 2 , (mod. on) 02706-050 figure 50. i avd d vs. f da t a vs. interpola t i o n ra te, p ll di sa b l ed 8 4 1 2 0 5 10 15 20 25 30 35 i clkv dd (ma) f data (mhz) 50 0 100 150 200 02706-051 figure 51. i clkvdd vs. f da t a vs. interpola t io n ra te, p l l di s a bled sleep/power-down modes (c o n tr ol r e g i ste r 00h, b i t 3 and b i t 4) the ad9777 p r o v ides tw o met h o d s f o r p r og ra mma b l e r e d u cti o n i n po w e r sa vi n g s . th e s l ee p m o de , w h en a c ti v a t e d , t u r n s o f f t h e d a c o u t p ut c u r r en ts b u t t h e r e s t o f t h e chi p re m a i n s f u nc t i o n i n g . wh e n c o m i ng out of sl e e p mo d e , t h e ad9777 immedia t e l y r e t u r n s t o f u l l o p era t io n. p o w e r - do wn mo d e , on t h e ot he r h a nd , tu r n s of f a l l an a l o g and d i g i t a l cir c ui tr y in t h e ad9777 excep t f o r th e s p i p o r t . w h en r e t u r n ing f r o m p o w e r - do wn mo de, e n o u g h clo c k c y cles m u st b e a l lo w e d to f l ush t h e dig i t a l f i l t ers o f r a ndo m d a t a a c q u ir e d d u ri n g th e po w e r - d o w n c y c l e . n o t e th a t o p t i m a l pe rf o r m a n c e w i t h th e p l l e n a b l e d i s a c h i e v ed w i th th e u c o i n th e p l l co n t r o l lo o p r u nnin g a t 450 m h z t o 550 m h z. t w o po rt d a ta inp u t mo d e th e di g i t a l da t a in p u t p o r t s ca n b e co n f i g ur e d a s tw o i n de p e nde n t p o r t s o r as a s i ng l e (on e - p o r t mo d e ) p o r t . i n t h e t w o - po r t m o d e , d a ta a t th e t w o i n p u t po rt s i s l a t c h e d i n t o th e ad977 7 on e v er y r i sing e d ge of t h e da t a r a t e c l o c k ( d a t a c l k ) . i n addi t i on, in t h e tw o - p o r t mo de, t h e ad977 7 can b e p r o g r a mm ed t o g e n e ra t e a n e x t e rn all y a v a i la b l e d a t a c l k f o r t h e p u r p ose o f da t a s y n c h r o n iza t i o n . th is da ta ra t e c l ock ca n be p r og ramm e d t o b e a v ai lab l e a t e i t h er p i n 8 ( d a t a c l k / p l l_lo c k ) o r p i n 5 3 ( s pi_s d o ). b e c a u s e p i n 8 c a n als o f u n c t i on as a pl l l o ck i n d i c a t o r w h e n t h e pll is enab l e d , t h er e a r e s e vera l op t i on s f o r conf igur in g pin 8 and pin 53. the fol l o w ing info r m a t i o n de s c r i b e s t h e s e o p t i ons. pll off (reg ist e r 4, b i t 7 = 0) reg i st er 3, b i t 7 = 0; d a t a clk o u t o f p i n 8. reg i st er 3, b i t 7 = 1; d a t a clk o u t o f p i n 53. pll on (reg ist e r 4, b i t 7 = 1) reg i st er 3, b i t 7 = 0, reg i s t er 1, b i t 0 = 0; p ll lo c k in dic a t o r o u t of pi n 8 .
ad9777 rev. c | page 30 of 60 reg i st er 3, b i t 7 = 1, reg i s t er 1, b i t 0 = 0; p ll lo c k in dic a t o r o u t o f p i n 53. reg i s t er 3, b i t 7 = 0, reg i s t e r 1, b i t 0 = 1; d a t a clk o u t o f p i n 8. reg i s t er 3, b i t 7 = 1, reg i s t e r 1, b i t 0 = 1; d a t a clk o u t o f p i n 53. i n on e-p o r t m o de , p2b14 and p2b15 f r o m in p u t da t a p o r t tw o a r e r e def i n e d as i q s e l a nd on epor t c l k , r e sp e c t i vely . the in p u t da t a i n one-p o r t mo de is ste e r e d to on e o f t h e tw o i n ter - na l d a t a cha n nels b a s e d o n t h e l o g i c le vel o f i q s e l. a clo c k sig n al , o n epor t c l k , is g e n e ra t e d b y t h e ad9777 in this m o de fo r t h e p u r p o s e o f da t a sy n c hr o n i z a t io n. onepor t c lk r u n s a t t h e i n p u t in t e rle a v e d d a t a ra t e , w h ich is 2 t h e d a t a r a t e a t t h e in ter n a l i n p u t t o ei t h er cha nne l. t e s t co n f i g ura t io n s sh o w in g t h e v a ri o u s c l oc k s th a t a r e r e q u i r ed a nd g e n e ra t e d b y th e ad9777 wi th t h e p ll enab led/dis a b l e d a nd in t h e on e-p o r t /tw o -p o r t m o des a r e g i v e n in f i gur e 101 t o f i gur e 104. j u m p er p o si tio n s n e eded t o op era t e th e ad9777 e v a l ua t i o n b o a r d i n t h es e m o de s a r e g i ven as wel l . pll enabled, two-por t mode (c o n tr ol r e g i ste r 02h, b i ts 6 to 0 and 04h, b i ts 7 t o 1) w i t h t h e p h as e-lo c k ed lo o p (p l l ) ena b led and th e ad9777 in t w o- po r t m o de , th e s p ee d o f c l k i n i s i n h e r e n t l y th a t o f th e in p u t da t a ra te . i n tw o-p o r t m o de , p i n 8 (d a t a c lk/p ll_ l o ck) can be p r og ra mm ed ( c o n tr ol reg i s t er 01h, b i t 0) t o f u n c t i on as ei t h er a lo ck i ndi ca to r fo r t h e i n t e r n a l pll o r as a c l o c k r u nnin g a t the in p u t da t a ra t e . w h en pin 8 is us ed as a c l oc k o u t p u t (d a t a c l k ), i t s f r eq ue n c y i s eq ual t o th a t o f clki n. da ta a t th e in p u t p o r t s is la t c h e d in t o t h e ad9777 o n th e r i sin g e d g e o f th e cl ki n. f i gur e 52 sh o w s t h e dela y , t od , in h e r e n t b e tw een t h e r i sin g e d ge o f clki n a n d th e r i sin g edg e o f d a t a clk, as w e l l as t h e s e t u p a nd h o ld r e q u ir em en ts f o r t h e da t a a t p o r t s 1 a n d 2. th e s e t u p a n d h o ld t i m e s g i ven in f i g u r e 52 a r e th e in p u t da ta tra n si ti o n s w i th r e spect t o c l k i n . n o t e t h a t i n tw o - p o r t m o de (pll en ab le d o r dis a b l e d ), t h e d a t a r a te a t t h e in ter p ola t io n f i l t er i n p u ts is t h e s a m e as t h e in pu t da t a r a t e a t po r t 1 a n d po r t 2 . th e d a c output s a m p l e r a te i n t w o - p o r t mo d e i s e q u a l to t h e cl o c k i n put r a te m u lt i p l i e d b y t h e i n te r p ol a t i o n r a te. i f z e ro s t uf f i n g is us ed, a n o t h e r fac t o r o f 2 m u s t b e in cl uded t o calc u l a t e t h e d a c s a m p le ra t e . dat a clk i n version (c o n tr ol r e g i ste r 02h, b i t 4) b y p r og ra mmin g this b i t, th e d a t a clk sig n al s h o w n in fi g u r e 5 3 c a n b e i n v e rt e d . w i t h i n versio n enable d, t od re f e r s to t h e t i me bet w een t h e ri s i n g ed g e o f c l kin a n d t h e fall in g ed g e o f d a t a c l k . n o ot he r e f f e c t on t i m i ng o c c u r s . t od t s t s = 0.0ns (max) t h = 2.5ns (max) t h clkin dataclk data at port s 1 and 2 02706-052 figure 5 2 . t i ming r e quir e m ents i n tw o-port input m o de with pll enab led dat a clk d r iver strength (c o n tr ol r e g i ste r 02h, b i t 5) the d a t a clk o u t p ut dr i v er s t r e n g t h is c a p a b l e o f dr i v in g >10 ma in t o a 3 30 ? lo ad while p r o v idin g a r i s e time o f 3 n s . f i gur e 53 sh o w s d a t a cl k dr ivin g a 330 ? r e sis t i v e lo ad a t a f r e q uen c y o f 50 mh z. by enab lin g t h e dr i v e s t r e n g t h o p t i o n (c o n t r ol r e g i s t er 02h, bi t 5), t h e a m pli t ude o f d a t a cl k u n der th es e con d i t io ns in cr eas e s b y a p p r o x ima t e l y 2 00 mv . ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 amp l itude (v ) 0 1 02 03 0 4 0 5 0 time (ns) delta approx. 2.8ns 02706-053 figure 53. datacl k d r iver c a pa bi li t y i n t o 3 3 0 at 5 0 m h z pll enabled, one-por t mode (c o n tr ol r e g i ste r 02h, b i ts 6 to 1 and 04h, b i ts 7 t o 1) i n on e- p o r t m o de, t h e i and q cha nnels r e cei v e t h eir da t a f r o m a n in t e rle a v e d str e a m a t dig i tal in p u t p o r t 1. the f u n c t i o n o f pin 32 is def i n e d as a n o u t p ut ( o nepor t c l k ) t h a t ge n e r a tes a clo c k a t t h e i n t e rle a v e d da t a ra te , w h ich is 2 t h e in t e r n a l i n p u t da ta ra t e o f t h e i a nd q c h a n n e l s . th e f r eq uen c y o f clkin is e q u a l to t h e i n te r n a l i n put da t a r a te of t h e i a n d q ch annel s .
ad9777 rev. c | page 31 of 60 the s e lec t ion o f th e da t a f o r th e i o r q c h a n n e l is det e r m in ed b y th e s t a t e o f t h e l o g i c lev e l a t p i n 31 (i qs el wh en t h e ad9777 is in on e-p o r t m o de) o n t h e r i sing edg e o f o n ep o r t c l k . u n der t h es e condi t i on s, i q s e l = 0 la t c h e s t h e da t a in t o t h e i cha nne l on t h e clo c k r i sin g e d ge , w h i l e i q s e l = 1 la t c h e s t h e da ta in t o the q c h a nne l . i t is p o s s i b le t o in v e r t t h e i and q s e lec t ion b y s e t t in g c o n t r o l reg i s t er 02h, b i t 1 to th e in ver t s t a t e (l og ic 1). f i gur e 54 i l l u s t ra t e s t h e t i min g r e q u ir emen t s fo r th e da t a in p u ts as w e l l as t h e i q s e l in p u t. n o t e tha t t h e 1 in t e r p ol a t ion ra t e is n o t a v a i la b l e in on e - p o r t mo de . th e d a c output s a m p l e r a te i n one - p o r t mo de i s e q u a l to c l k i n m u lt i p l i e d b y t h e i n te r p ol a t i o n r a te. i f z e ro st u f f i ng i s u s e d , a n ot he r f a c t or of 2 m u st b e i n clu d e d to c a l c u l a t e t h e d a c sa m p l e ra t e . oneportcl k in versio n (c o n tr ol r e g i ste r 02h, b i t 2) b y p r ogra mming this b i t, t h e onepo r tclk s i g n al sh o w n in f i g u re 5 4 c a n b e i n ve r t e d . w i t h i n ve rs i o n e n abl e d, t od re f e r s to t h e del a y b e tw e e n t h e r i sin g e d g e o f t h e ext e r n al clo c k and t h e f a l l ing e d ge of one p or tc l k . the s e t u p and hol d t i me s , t s a nd t h , a r e w i t h r e s p e c t t o t h e f a l l in g e d g e o f onepo r tclk. ther e is n o o t her ef fe c t o n t i mi n g . oneportcl k dri v er st rength the dr i v e ca p a b i li ty o f o n epo r t c l k is iden t i cal t o tha t o f d a t a cl k in t h e tw o-p o r t m o de . ref e r t o f i g u r e 53 f o r p e r f o r ma n c e u nder lo ad co ndi t i o n s. t od t s t iqs t iqh t od = 4.0ns (min) to 5.5ns (max) t s = 3.0ns (max) t h = ? 0.5ns (max) t iqs = 3.5ns (max) t iqh = ? 1.5ns (max t h clkin oneportclk iqsel i and q interleaved input data at port 1 02706-054 figure 54. t i ming r e quirements in on e-port input mo de, wi th the p l l ena b l e d iq pa iring (c o n tr ol r e g i ste r 02h, b i t 0) i n on e- p o r t m o de, t h e in terle a ve d da t a is l a tch e d i n to t h e ad9777 in t e r n a l i a nd q c h a n ne ls in p a irs. th e o r der o f h o w t h e p a irs a r e la tch e d i n ter n a l ly is def i n e d b y t h i s co n t r o l r e g i ste r . the fol l o w in g is a n exa m ple o f t h e ef fe c t t h is has o n in co min g in t e rle a ve d d a t a . gi ven t h e fol l o w i n g i n terle a ve d da t a st r e am, w h er e t h e da t a indi ca t e s t h e v a l u e w i t h r e sp e c t t o f u l l s c ale: i q i q i q i q i q 0 . 5 0 . 5 1 1 0 . 5 0 . 5 0 0 0 . 5 0 . 5 w i t h t h e con t r o l r e g i s t er s e t t o 0 (i f i rs t), t h e da t a a p p e a r s a t t h e in t e r n a l cha n nel in p u ts i n t h e fol l o w in g o r der i n t i m e : i c h a n n e l 0 . 5 1 0 . 5 0 0 . 5 q channe l 0 . 5 1 0 . 5 0 0 . 5 w i th th e c o n t r o l r e gi s t e r s e t t o 1 ( q fi r s t ) , t h e d a t a a p pe a r s a t t h e in t e r n a l channe l i n p u ts i n t h e fol l o w in g o r der in t i m e : i c h a n n e l 0 . 5 1 0 . 5 0 0 . 5 x q channe l y 0 . 5 1 0 . 5 0 0 . 5 the val u es x and y r e p r es en t t h e n e xt i val u e and t h e p r e v io us q val u e i n t h e s e r i es. pll disabled, two-port mode w i th th e p l l d i s a b l e d , a c l oc k a t t h e d a c o u t p u t r a t e m u s t b e a p p l ie d t o cl ki n. i n t e r n al c l o c k dividers in t h e ad9777 syn - t h esize t h e d a t a clk sig n a l a t p i n 8, w h ich r u n s a t t h e i n p u t d a t a r a te and can b e us e d to sy nchr o n iz e t h e i n p u t da t a . d a t a is la t c h e d in t o in p u t p o r t 1 a n d p o r t 2 o f th e ad9 777 o n the r i sing ed g e o f d a t a cl k . d a t a c l k s p eed i s d e f i n e d a s th e s p e e d o f clkin di vide d b y t h e in ter p ola t io n r a te. w i t h zer o st uf f i n g en- a b le d , th is di vi si o n in cr e a ses b y a fac t o r o f 2. fi g u r e 5 5 il l u s t ra t e s t h e del a y b e tw e e n t h e r i sin g e d ge o f clkin and t h e r i sin g e d ge o f d a t a clk, as w e l l as t s an d t h in t h is m o d e . the p r o g r a mma b l e m o des d a t a c l k i n versio n a nd d a t a c l k dr i v er st r e n g t h des c r i b e d i n t h e pll ena b le d , t w o - p o r t m o de secti o n ha v e i d en ti cal fun c ti o n a l i t y w i th t h e p l l d i sa b l e d . the da t a r a te c l k cr e a te d b y d i vi di n g do w n t h e d a c clo c k i n this mo de ca n b e p r og ra mm ed (via reg i st er x03h, b i t 7) t o be o u t p u t f r o m the s p i_s d o p i n, r a t h er tha n t h e d a t a cl k p i n. i n s o me a p pli c a t io n s , t h is m a y i m p r o v e com p lex ima g e r e j e c - ti o n . t od in cr eas e s b y 1.6 n s w h en s p i_s d o is us ed as da ta r a t e cl o c k ou t.
ad9777 rev. c | page 32 of 60 t od t s t h t od = 6.5ns (min) to 8.0ns (max) t s = 5.0ns (max) t h = ? 3.2ns (max) clkin dataclk data at port s 1 and 2 02706-055 figure 5 5 . t i ming r e quir e m ents i n tw o-port input m o de, with pll dis a bled pll disabled, one-port mode i n on e-p o r t m o de , da ta is r e ceiv ed in t o t h e ad9777 as a n in t e rlea ved s t r e a m o n p o r t 1. a c l o c k sig n al (onepo r t clk), r u nnin g a t t h e i n terle a ve d da t a r a te, w h ich is 2 t h e in pu t da t a r a te o f t h e i n ter n a l i a nd q channels, is a v a i l a ble fo r da t a sy n c hr o n iz a t io n a t pin 32. w i t h pll dis a b l e d , a c l o c k a t t h e d a c o u t p u t ra t e m u st b e a p plie d t o clkin. i n t e rnal di viders syn t h e size th e o n ep o r t c lk si g n al a t pin 32. th e s e le c t io n o f t h e da t a f o r t h e i o r q c h a n n e l is deter - min e d b y t h e s t a t e o f t h e l o g i c le v e l a p plie d t o p i n 31 (i qs el w h en th e ad9777 is in o n e-p o r t m o de) o n th e r i sin g ed g e o f one p or tc l k . u n de r t h e s e c o n d i t ions , i q s e l = 0 l a tche s t h e d a ta i n t o th e i c h a n n e l o n th e c l oc k ri si n g ed g e , wh ile i q s e l = 1 la t c h e s th e d a ta i n t o th e q c h a n n e l . i t i s pos s i b le t o i n v e r t th e i a n d q s e l e c t i o n b y s e t t i n g c o n t r o l r e g i ster 02 h, bi t 1 t o t h e i n ver t st a t e (logi c 1). fi g u re 5 6 ill u s t ra t e s th e ti m i n g r e q u i r e m e n t s f o r th e d a ta in p u ts as w e l l as t h e i q s e l in p u t. n o t e t h a t t h e 1 in t e r p ola t io n ra t e is n o t a v a i la b l e in t h e o n e-p o r t m o de . on e-p o r t m o de is v e r y us ef u l wh en in t e r f ac in g wi th de vices , s u c h as t h e ana l og devices ad6622 o r ad6623 tra n smi t sig n a l p r o c ess o rs, in w h ich tw o d i g i t a l d a t a chan n e ls h a v e b e e n i n t e r - l e a v ed (m ul ti p l e x ed ) . t h e p r o g r a m m a b l e m o d e s o n ep o r t c l k in v e rsio n, onepor t c lk dr i v er st r e n g t h , a n d i q p a ir in g des c r i b e d in t h e p l l e n a b l e d , o n e - p o r t mo d e s e c t io n ha ve i d e n ti cal fun c ti o n ali t y w i th th e p l l d i sa b l e . t od t s t iqs t iqh t h t od = 4.0ns (min) to 5.5ns (max) t od = 4.7ns (max) t s = 3.0ns (max) t h = ? 1.0ns (max) t iqs = 3.5ns (max) t iqh = ? 1.5ns (max) (typ specs) clkin iqsel oneportclk i and q interleaved input data at port 1 02706- 056 figure 5 6 . t i ming r e quir e m ents i n on e-port input m o de, with pll dis a bled digi tal fil t er modes the i an d q da t a p a th s o f t h e ad9777 ha v e their o w n inde p e n d e n t ha lf-b an d f i r f i l t e r s. e a ch da t a p a t h co n s ists o f t h r e e fir f i l t ers , p r o v i d in g u p to 8 in t e r p ola t i o n fo r e a ch cha nnel. t h e r a te o f in ter p ola t i o n is deter m i n e d b y t h e st a t e o f c o n t r o l reg i s t er 01h, b i t 7 an d b i t 6. f i gur e 2 to f i gur e 4 sh o w th e r e sp o n s e o f th e dig i tal f i l t ers w h en t h e ad9 777 is s e t t o 2, 4, a n d 8 m o des. th e f r e q uenc y axes o f t h es e g r a p h s ha v e been n o r m alize d t o t h e in p u t da ta ra t e o f t h e d a c. a s t h e g r a p h s sh o w , t h e dig i t a l f i l t ers c a n p r o v ide g r e a ter t h a n 75 db o f o u t-o f -b and r e j e c t io n. an o n lin e t o ol is a v a i la b l e f o r q u i c k a n d eas y a n al ys is o f th e ad9777 in t e r p ol a t io n f i l t e r s in th e va r i o u s m o des. th e link ca n be acces s ed a t h t t p ://w w w .a nalog.c o m/analog_ro o t / s t a t ic/ t e c h s u p p o r t/d e si g n t o o l s/in t e rac t i v et o o ls/dac/ad9 777ima g e .h tml . amplitu d e modula tion give n t w o s i ne w a ve s a t t h e s a me f r e q u e nc y but w i t h a 9 0 phas e dif f er en ce , a p o i n t o f vi e w in t i m e ca n b e t a k e n s u ch t h a t t h e wa v e fo r m t h a t le ads in phas e is cosin u s o i d al a nd t h e wa v e f o r m tha t l a gs is sin u s o idal. anal ysis o f co m p lex va r i ab les st a t es t h a t t h e c o sin e w a vefo r m ca n b e def i ne d as ha vin g r e a l posi ti v e a n d n e ga ti v e f r eq ue n c y co m p o n e n ts, wh ile t h e sin e w a ve for m c o ns i s t s of i m ag i n ar y p o s i t i ve and ne g a t i ve f r e q u e nc y ima g es. this is sh o w n g r a p hi ca l l y in t h e f r e q uenc y do ma in i n f i gur e 57.
ad9777 rev. c | page 33 of 60 e ?j t /2j e ?j t /2j e ?j t /2 e ?j t /2 dc dc cosine sine 02706-057 fig u re 5 7 . r e al and im ag in ary c o mpo n ent s of si nusoi d al a n d c o s i nusoi d al wa vef o rm s a m pl itu d e m o du l a t i ng a b a s e b a n d s i g n a l w i t h a s i ne or a c o s i n e co n v ol v e s t h e b a s e b a nd sig n al wi t h t h e m o d u l a t i n g ca r r i er in t h e f r e q ue n c y do ma in. a m pli t u d e s c ali n g o f t h e m o d u la t e d sig n al r e d u ces t h e p o si ti v e and n e g a ti v e f r e q ue n c y ima g es b y a fac t o r o f 2. this s c a l in g is v e r y im p o r t a n t in t h e dis c ussio n o f th e v a ri o u s m o d u la ti o n m o d e s. the phas e rel a t i o n shi p o f t h e mo d u l a te d sig n a l s is dep e nden t o n w h et h e r t h e m o d u l a t i n g ca r r ier is sin u s o i d a l o r cosin u s o ida l , ag ai n w i t h re sp e c t to t h e re f e re nc e p o i n t of t h e v i e w e r . e x a m ples o f sine a nd co si n e mo d u l a t i on a r e g i ven i n f i gur e 5 8 . dc sinusoidal modulation cosinusoidal modulation dc ae ?j t /2j ae ?j t /2j ae ?j t /2 ae ?j t /2 02706-058 f i g u re 58. bas e band sig n al, a m plit ude m o dulated wi th sin e and cosine carrier s
ad9777 rev. c | page 34 of 60 modula ti on, n o in te rpolati o n w i t h c o n t r o l reg i s t er 01h, bi t 7 a nd b i t 6 s e t to 00, th e in t e r p ol a t ion f u n c tion o n t h e ad9777 is dis a b l ed . f i gur e 59 t o f i g u re 6 2 s h ow t h e d a c output sp e c t r a l ch ar a c te r i st i c s of t h e ad9777 in t h e va r i o u s m o d u l a tio n m o des , al l wi th t h e in t e r p ol a t ion f i l t ers dis a b l e d . t h e m o d u l a t i on f r e q uen c y is det e r m in ed b y t h e sta t e o f c o n t r o l reg i s t er 01h, b i ts 5 an d 4. the t a l l r e c t an g l es r e p r es en t t h e dig i t a l do ma i n s p e c t r u m o f a ba se ba n d si gnal o f n a rr o w ba n d w id t h . by co m p a r in g t h e dig i t a l do main sp e c t r um to t h e d a c s i n(x ) /x r o l l -o f f , a n est i ma te can b e mad e fo r t h e cha r ac ter i s- ti cs r e q u i r ed f o r th e d a c r e co n s tr ucti o n f i l t e r . n o t e also , pe r t h e pr e v i ou s d i s c u s s i on on a m pl itu d e mo d u l a t i on , t h at t h e s p ec tral com p on en ts (w h e r e mo d u l a tion is s e t t o f s /4 o r f s /8) a r e s c ale d b y a fac t o r o f 2. i n t h e si t u a t ion w h er e t h e m o d u l a t i on i s f s / 2 , t h e m o d u la t e d spectral co m p o n en t s ad d co n s tr ucti v e l y , a nd t h er e is n o s c al in g ef fe c t . t h e e f fe c t s o f d i g i t a l m o du l a t i on on d a c o u tpu t sp e c t r u m , inte r p o l at i o n d i s a b l e d ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) 02706-059 fig u re 5 9 . n o i n t e r p ol at i o n, m o dul a t i on d i s a b l ed ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) 02706-060 fig u re 6 0 . n o i n t e r p ol at i o n, m o dul a t i on = f da c /2 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) 02706-061 fig u re 6 1 . n o i n t e r p ol at i o n, m o dul a t i on = f da c /4 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) 02706-062 fig u re 6 2 . n o i n t e r p ol at i o n, m o dul a t i on = f da c /8
ad9777 rev. c | page 35 of 60 modula ti on, in terp olati o n = 2 w i t h c o n t r o l reg i s t er 01h, bi t 7 a nd b i t 6 s e t to 01, th e in t e r p ol a t ion ra t e o f t h e ad977 7 is 2. m o d u la t i o n is achi e v e d b y m u l t i p l y in g succes si v e s a m p les a t t h e in ter p ola t ion f i l t er o u t p u t b y t h e s e q u en c e (+1, ?1). f i gur e 63 t o f i gur e 66 r e p r es en t t h e s p ec tral r e s p o n s e o f th e ad9777 d a c o u t p u t wi t h 2 in ter p ol a t ion i n t h e va r i o u s m o d u l a t i on mo des to a na r r o w b a nd b a s e b a n d sig n al (a ga i n , t h e t a l l r e c t a n g l es in t h e g r a p hic). the adva n t a g e o f in t e r p ol a t io n b e com e s cle a r i n f i gur e 63 t o f i gur e 66, w h ere i t c a n b e s e en t h a t t h e ima g es t h a t w o u l d n o r m a l ly a p p e ar in t h e sp e c t r um a r o u nd t h e s i g n if ica n t p o i n t i s t h a t t h e in t e r p ola t ion f i l t er i n g is do ne p r io r t o t h e dig i t a l mo d u l a tor . fo r t h i s r e a s o n , a s fi g u r e 6 3 t o fi g u r e 6 6 s h o w , t h e p a s s b a n d o f t h e in t e r p ola t io n f i l t ers can b e f r e q uen c y shif te d , g i ving t h e e q ui va le n t o f a hig h -p ass d i g i t a l f i l t er . n o t e t h a t w h en usin g t h e f s / 4 m o d u la ti o n m o d e , th e r e i s n o t r ue sto p b a nd a s t h e b a n d e d ge s co in c i de w i t h e a ch o t h e r . i n th e f s / 8 mo d u l a t i on mo d e , am p l i t u d e s c a l i n g o c c u rs o v e r on ly a po r t i o n o f th e di gi tal f i l t e r pa s s ba n d d u e t o co n s tr ucti v e a d di ti o n o v e r j u s t th a t secti o n o f th e ba n d t h e e f fe c t s o f d i g i t a l m o du l a t i on on d a c o u tpu t sp e c t r u m , inte r p o l at i o n = 2 x ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) f out ( f data ) 0.5 0 1.0 1.5 2.0 02706-063 fig u re 6 3 . 2 int e r p ol at i o n, m o dul a t i on = d i s a bl ed ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) f out ( f data ) 0.5 0 1.0 1.5 2.0 02706-064 fig u re 6 4 . 2 int e r p ol at i o n, m o dul a t i on = f da c /2 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 0.5 0 1.0 1.5 2.0 02706-065 fig u re 6 5 . 2 int e r p ol at i o n, m o dul a t i on = f da c /4 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) f out ( f data ) 0.5 0 1.0 1.5 2.0 02706-066 fig u re 6 6 . 2 int e r p ol at i o n, m o dul a t i on = f da c /8
ad9777 rev. c | page 36 of 60 modula ti on, in term odulat io n = 4 w i t h c o n t r o l reg i s t er 01h, bi t 7 a nd b i t 6 s e t to 10, th e in t e r p ol a t ion ra t e o f t h e ad977 7 is 4. m o d u la t i o n is achi e v e d b y m u l t i p l y in g succes si v e s a m p les a t t h e in ter p ola t ion f i l t er o u t p u t b y t h e s e q u en c e (0, +1, 0, ?1). f i g u re 6 7 to f i g u re 7 0 re pre s e n t t h e sp e c t r a l re s p ons e of t h e ad9777 d a c ou t p u t wi t h 4 in t e r p ola t io n in th e va r i o u s m o d u l a t i on m o des to a na r r o w b a nd b a s e b a n d sig n a l . t h e e f fe c t s o f d i g i t a l m o du l a t i on on d a c o u tpu t sp e c t r u m , inte r p o l at i o n = 4 x ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-067 4 figure 6 7 . 4x inte rp ol ati o n, m o dul a ti o n dis a bled ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-068 4 figure 6 8 . 4x inte rp ol ati o n, m o dul a ti o n = f da c /2 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-069 4 figure 6 9 . 4x inte rp ol ati o n, m o dul a ti o n = f da c /4 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-070 4 figure 7 0 . 4x inte rp ol ati o n, m o dul a ti o n = f da c /8
ad9777 rev. c | page 37 of 60 modula ti on, in term odulat io n = 8 w i t h c o n t r o l reg i s t er 01h, bi ts 7 a nd 6, s e t t o 11, th e in t e r p ol a t ion ra t e o f t h e ad977 7 is 8. m o d u la t i o n is achi e v e d b y m u l t i p l y in g succes si v e s a m p les a t t h e in ter p ola t ion f i l t er o u t p u t b y t h e s e q u en c e (0, +0.707, +1, +0.707, 0, C0.707, ?1, +0.707). f i gur e 71 t o f i gur e 74 r e p r es en t t h e s p ec tral r e s p o n s e o f th e ad9777 d a c o u t p u t wi t h 8 in t e r p ola t io n in t h e va r i o u s m o d u l a t i on m o des to a na r r o w b a nd b a s e b a n d sig n a l . l o okin g a t f i gu r e 59 t o f i gur e 75, th e us er ca n s e e h o w hig h er in t e r p ol a t ion ra t e s r e d u ce t h e c o m p lexi ty o f t h e r e co n s t r uc t i o n f i l t e r n e e d e d at t h e d a c o u t p u t . i t a l s o b e c o m e s ap p a r e nt t h at t h e ab i l it y to mo d u l a te b y f s /2, f s /4, o r f s /8 adds a deg r e e o f f l e x ib i l it y i n f r e q u e nc y pl an n i n g the ef f e c t s of t h e dig i ta l m o du l a ti o n on the d a c o u t p ut sp e c tr um, i n t e r p ol a t i o n = 8 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-071 4 fig u re 7 1 . 8 int e r p ol at i o n, m o dul a t i on d i s a b l ed ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) f out ( f data ) 1 02 3 02706-072 4 figure 7 2 . 8x inte rp ol ati o n, m o dul a ti o n = f da c /2 ? 100 ?80 ?60 ?40 ?20 0 amp l itude (dbfs ) 4 3 12 05 6 f out ( f data ) 02706-073 7 8 figure 7 3 . 8x inte rp ol ati o n, m o dul a ti o n = f da c /4 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbfs ) 4 3 12 05 6 7 f out ( f data ) 02706-074 8 figure 7 4 . 8x inte rp ol ati o n, m o dul a ti o n = f da c /8
ad9777 rev. c | page 38 of 60 zero stuffing (c o n tr ol r e g i ste r 01h, b i t 3) a s sho w n in f i g u r e 75, a 0 o r n u l l in t h e o u t p u t f r eq uen c y re sp ons e of t h e d a c ( a f t e r i n te r p o l a t i o n , mo du l a t i o n , a n d d a c r e co n s tr ucti o n ) occur s a t t h e f i nal d a c sa m p le ra t e (f dac ). t h is i s d u e to t h e i n h e re n t si n ( x ) / x ro l l - o f f re sp ons e i n t h e d i g i t a l - t o -a nalog co n v e r sio n . i n a p pli c a t io n s w h er e t h e desir e d f r e - qu e n c y c o n t e n t i s b e l o w f dac /2, t h is ma y n o t b e a p r ob lem. n o te t h at at f dac /2 t h e los s d u e t o s i n(x)/x is 4 db . i n dir e c t rf a p p l i- ca ti o n s, th i s r o ll- o f f m a y be p r ob le m a ti c d u e t o th e in cr ea se d p a ss-b an d am pl i t u d e va r i a t io n as w e l l as t h e r e d u ce d am pl i t u d e o f t h e des i r e d si g n a l . c o n s ider an a p p l ica t ion w h er e th e dig i tal da t a in t o t h e ad9777 r e p r es en ts a b a s e b a nd sig n a l a r o u nd f dac /4 wi t h a p a s s band o f f dac /10. th e r e c o n s tr uc t e d sig n al o u t o f the ad9777 w o u l d exp e r i ence o n l y a 0.75 db am pli t ude va r i a t ion o v er i t s p a s s ba n d . h o w e v e r , th e i m a g e o f t h e sa m e si gn al oc c u rri n g a t 3 f dac /4 su f f e r s f r om a p a ss - b and f l a t ne ss v a r i a t i o n of 3 . 9 3 db . this im a g e m a y b e t h e desir e d s i g n a l i n a n if a p plica t io n usin g o n e o f t h e va r i ous m o d u la tio n m o des in t h e ad9777. this r o l l - o f f o f ima g e f r eq uen c ies can b e s e en i n f i gur e 59 t o f i gur e 74, w h er e t h e ef fe c t o f t h e i n t e r p ol a t io n an d mo d u l a t i o n ra t e is ap p a r e nt a s w e l l . ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 10 s i n (x )/ x ro ll-o ff (dbfs ) f out , normalized to f data with zero stuffing disabled (hz) 0.5 0 1.0 1.5 2.0 zero stuffing enabled zero stuffing disabled 02706-075 fi gur e 75 . effect o f zer o stuffi ng o n dacs sin(x)/ x response t o im p r o v e up on t h e p a s s - b an d f l a t n e s s o f t h e desir e d i m a g e, t h e zer o st uf f i n g m o de can b e e n a b le d b y s e t t ing t h e co n t r o l r e g i s t er b i t t o a l o g i c 1. this o p tio n in cr eas e s t h e ra t i o o f f dac /f da t a b y a fac t o r o f 2 b y do ub lin g t h e d a c s a m p le ra te an d in s e r t ing a mids cale s a m p le (tha t is, 1000 0000 0000 0000) a f t e r e v er y da t a s a m p le o r ig ina t in g f r o m t h e i n t e r p ol a t io n f i l t er . this is im p o r t an t as i t a f f e c t s th e pll divider ra t i o n e eded t o k e ep th e v c o wi thi n i t s o p t i m u m sp eed ra n g e . n o t e th a t t h e z e r o s t uf f i n g tak e s pla c e in t h e di gi ta l si gn al c h a i n a t th e o u t p u t o f th e d i g i tal m o d u la t o r , be f o r e th e d a c . the n e t ef fe c t is t o in cr e a s e t h e d a c o u t p u t s a m p le ra t e b y a f a ct o r o f 2 w i th th e 0 i n th e s i n ( x ) / x d a c t r a n s f e r fu n c t i o n o c c u r r in g a t t w i c e t h e o r ig ina l f r e q uen c y . a 6 d b loss in a m p l i t ude a t l o w f r eq ue n c i e s i s al so ev id en t , a s ca n be s e e n i n f i gur e 76. i t is im p o r t a n t to r e a l ize t h a t t h e zer o st uf f i n g o p t i o n b y i t s e lf do es n o t cha n g e t h e lo ca t i o n o f t h e ima g es b u t ra t h er t h eir a m pli t ud e, p a ss -b an d f l a t n e ss, a nd r e l a t i ve w e i g h t i n g. f o r in s t an c e , i n t h e p r e v io us exam ple , t h e p a s s -b a nd a m pl i t u d e f l a t n e s s o f t h e i m a g e a t 3 f da t a /4 is no w im p r o v ed t o 0.59 db while t h e sig n al lev e l has in cr eas e d slig h t l y f r o m ?10.5 db fs to C8.1 db fs. interpola t ing (com plex mix mo de) (c o n tr ol r e g i ste r 01h, b i t 2) i n t h e co m p lex m i x m o d e , t h e tw o d i gi tal m o d u la t o r s o n th e ad9777 a r e co u p led t o p r o v ide a co m p lex m o d u la tion f u nc tion. i n co n j un cti o n w i th a n ext e rn al q u ad ra t u r e m o d u la t o r , th i s co m p lex m o d u l a tio n ca n be us e d t o r e alize a tran smi t ima g e re j e c t i o n arch it e c tu re. t h e c o mp l e x mo d u l a t i o n f u nc t i on c a n b e p r ogra mm ed f o r e +j t or e ?j t t o g i v e u p p e r o r lo w e r ima g e re j e c t i o n . a s i n t h e re a l mo d u l a t i on mo d e , t h e mo d u l a t i o n f r eq uen c y ca n b e p r og ra mmed via t h e s p i p o r t f o r f dac /2, f dac /4, a nd f dac / 8 , w h er e f dac r e p r es en ts t h e d a c o u t p ut ra te . operations on c o mplex signal s t r ul y co m p lex s i gn als ca nn o t b e r e aliz ed o u t s id e o f a co m p u t er si m u la ti o n . h o w e v e r , tw o da t a c h a n n e ls, bo th co n s i s ti n g o f r e al d a t a , can b e def i n e d as t h e r e a l a nd im a g ina r y co m p on e n ts o f a co m p lex signal . i (r eal) a n d q (ima gina r y ) da ta p a th s a r e o f t e n def i n e d t h i s w a y . by usin g t h e a r chi t e c t u r e d e f i ne d i n f i gur e 76, a sys t em t h a t op era t es o n com p lex sig n als ca n b e r e ali z e d , g i vin g a com p le x (r e a l a n d imag ina r y) o u t p u t . i f a c o m p l e x mo d u l a t i on f u nc t i on ( e +j t ) is desir e d , t h e r e a l and ima g ina r y co m p o n e n ts o f t h e s y s t em co r r es p o nd t o t h e r e al and ima g ina r y co m p o n e n ts o f e +j t o r cost a n d sint. a s f i gur e 77 s h o w s, t h e co m p lex m o d u la t i on f u n c tio n ca n be r e al ize d b y a p pl ying t h es e c o m p on en ts t o t h e st r u c t ur e o f t h e com p lex sy stem def i n e d in f i gur e 76. a(t) = (c + jd) b(t) c(t) b(t) + d b(t) b(t) a(t) + c b(t) input output input output complex filter imaginary 02706-076 fig u re 7 6 . r e al iz at i o n of a c o mpl e x sy s t em
ad9777 rev. c | page 39 of 60 input (real) output (real) output (imaginary) input ( imaginary ) 90 e ?j t = cos t + jsin t 02706-077 fi gu r e 77 . im plem en ta ti on o f a com p le x mo dul a to r complex modulation and image rejection of baseband signals i n trad i t i o nal tra n sm i t a p p l ica t io n s , a t w o- s t e p u p co n v e r si o n i s do ne i n w h ich a b a s e b a n d sig n a l is m o d u l a te d b y o n e ca r r i er to a n if (in t er m e d i a t e f r e q ue n c y ) a nd t h en mo d u l a te d a s e cond tim e t o t h e tra n sm i t f r eq ue n c y . a l t h o u g h th i s a p p r oa c h h a s s e v e ra l b e n e f i ts, a ma jo r dra w b a c k is tha t tw o ima g es a r e cr e a t e d n e a r t h e tra n smi t f r e q uen c y . onl y o n e ima g e i s n e e d e d , t h e o t h e r b e in g a n exac t d u plica t e . u n less th e un wa n t e d ima g e is f i l t e r e d , typ i ca l l y wi t h a n a l og co m p o n en ts, tra n smi t p o w e r i s wast e d a n d t h e us a b le b a n d wid t h a v a i la b l e in t h e sys t em is r e d u ce d . a m o r e ef f i cien t met h o d o f su pp r e s s in g t h e u n wa n t e d ima g e ca n be a c h i ev ed b y us i n g a co m p l e x m o d u l a t o r f o ll o w ed b y a q u a d ra t u r e m o d u l a t o r . f i gur e 78 is a b l o c k d i ag ra m o f a q u adra t u r e m o d u l a t o r . n o t e tha t i t is in fac t t h e r e al o u t p u t ha lf o f a c o mp l e x m o d u l a t o r . t h e c o mp l e t e u p c o n v e r s i o n c a n ac t u al l y b e r e fer r e d t o as tw o com p lex u p con v ersio n s t a g es, t h e re a l output of w h i c h b e c o me s t h e t r ans m itte d s i g n a l . input (real) output input (imaginary) 90 cos t sin t 02706-078 figure 78. qu adrat u re m o dulation the en t i r e u p con v ersio n f r o m b a s e b a nd t o t r a n smi t f r e q uen c y is r e p r es en t e d g r a p hical l y i n f i g u r e 79. the r e s u l t in g sp e c t r um s h o w n i n f i gur e 79 r e p r es en ts t h e com p lex da t a co n s is t i n g o f t h e b a s e b a nd r e a l a nd im a g ina r y cha nnels, no w m o d u l a te d o n to o r t h o g o n a l (co s ine an d nega t i ve sine) ca r r iers a t t h e t r a n sm i t f r eq ue n c y . i t i s im po r t a n t t o r e m e m b e r tha t in th i s a p p l ica t i o n (tw o b a s e b a nd d a t a chan n e ls), t h e im a g e r e j e c t io n is n o t dep e nden t o n t h e da ta a t ei t h er o f th e ad9777 in p u t c h a n ne ls. i n fac t , i m a g e r e je c t io n s t i l l o c c u rs wi t h e i t h er o n e o r b o t h o f th e ad9777 in p u t c h a n n e ls ac t i v e . n o te tha t b y c h a n g i n g t h e sig n o f the sin u s o ida l m u l t i p l y ing t e r m in t h e com p lex m o d u l a to r , t h e u p p e r sideb a nd ima g e co u l d h a ve b e e n su p p r ess e d w h i l e p a ssin g t h e lo w e r o n e . this is e a si ly do n e in th e ad9777 b y s e lec t in g t h e e +j t b i t ( r eg ist e r 0 1 h, bi t 1). i n pu rely c o m p l e x te r m s , f i g u re 7 9 re pre s e n t s t h e t w o - s t age up c o n v e r s i on f r om c o m p l e x b a s e b a n d to c a r r i e r .
ad9777 rev. c | page 40 of 60 real channel (out) imaginary channel (out) a/2 ?b/2j b/2j ?a/2j a/2j ?f c 1 f c f c ?f c ?f c ?f c f c ?f c a/2 b/2 b/2 complex modulator to quadrature modulator real channel (in) imaginary channel (in) a dc b dc a/4 + b/4j a/4 ? b/4j a/4 + b/4j a/4 ? b/4j ?a/4 ? b/4j a/2 + b/2j a/2 ? b/2j a/4 ? b/4j a/4 + b/4j ?a/4 + b/4j ?f q ? f c ?f q + f c ?f q 2 ?f q f q ?f q f q f q ? f c f q + f c f q quadrature modulator out real imaginary rejected images 1 f c = complex modulation frequency 2 f q = quadrature modulation frequency 02706-079 figure 7 9 . t w o-st a g e upconv ersi on a n d r e sulting im age r e ject ion
ad9777 rev. c | page 41 of 60 complex baseband signal output = real = real frequency 1 1/2 1/2 ? 1? 2d c e j( 1 + 2)t 1 + 2 02706-080 figure 8 0 . t w o-st a g e co mpl e x upc o n v ersio n image rejectio n a n d sideband suppressions of m o dulated c a rriers a s sho w n i n f i g u r e 79, ima g e r e j e c t io n ca n b e a c hie v e d b y a p p l ying bas e band da t a t o t h e ad9777 a nd f o l l o w in g t h e ad9777 wi t h a q u adra t u r e m o d u l a t o r . t o p r o c es s m u l t i p le ca r r i ers w h i l e st i l l ma in t a in in g i m a g e r e j e c t c a p a b i l i ty , e a ch ca r r i er m u s t be co m p lex m o d u l a t e d . a s f i gur e 80 s h o w s, sin g le o r m u l t i p le co m p lex m o d u la t o rs ca n be us e d t o syn t h e size co m p lex ca r r i ers. th es e com p le x ca r r i ers a r e t h en s u mme d and a p p l ie d t o t h e real an d ima g inar y in p u ts o f the ad9777. a sys t em in whic h m u l t i p le bas e ba nd sig n als a r e co m p lex m o d u la te d a n d t h en a p plie d to t h e ad9777 r e a l a n d ima g ina r y in p u ts, fo l l o w e d b y a q u adra t u r e m o d u la t o r , is sh o w n in fi g u r e 8 2 , wh i c h also d e scri be s th e tra n sf e r fun c ti o n o f th is sys t e m a n d t h e s p ectral o u t p u t . n o t e t h e si m i la ri t y o f th e tra n sf e r fun c ti o n s g i ven i n f i gur e 82 a nd f i gur e 8 0 . f i gur e 82 add s a n ad di t i o n a l co m p lex m o d u la t o r s t a g e f o r s u mmin g m u l t i p le ca r r ier s a t t h e ad9777 in p u ts . i n addi tio n , as in f i gur e 79, t h e ima g e r e jec t ion is n o t dep e nde n t o n t h e r e a l o r i m a g ina r y b a s e b a nd da t a o n an y cha nnel. i m a g e r e j e c t io n on a cha nnel o c c u rs if ei t h er t h e r e a l o r ima g ina r y d a t a , o r b o t h , is p r es en t on t h e b a s e b a nd cha n ne l. i t is im p o r t a n t to r e m e m b er t h a t t h e m a g n i t ud e o f a co m p lex sig n al can b e 1. 414 th e ma g n i t ude o f i t s r e al or ima g ina r y co m p on en ts. d u e t o this 3 db in cr eas e in sig n a l a m p l i t ude , t h e r e al a nd ima g ina r y in p u ts t o t h e ad9777 m u s t be k e p t a t leas t 3 db b e lo w f u l l s c ale w h en op er a t in g w i t h t h e c o m p lex mo d u l a tor . o v e r r a ng i n g i n t h e c o m p l e x mo d u l a tor re su lt s i n sev e r e d i s t o r ti o n a t th e d a c o u t p u t . baseband channel 1 real input baseband channel 2 real input baseband channel n real input imaginary input imaginary input imaginary input complex modulator 1 complex modulator 2 complex modulator n r(1) r(1) r(2) r(2) r(n) r(n) multicarrier real output = r(1) + r(2) + . . .r(n) (to real input of ad9777) multicarrier imaginary output = i(1) + i(2) + . . .i(n) (to imaginary input of ad9777) r(n) = real output of n i(n) = imaginary output of n 02706-081 fi gur e 81 . synthesis o f mul t icar ri er com p lex si gnal multiple baseband channels multiple complex modulators frequency = 1 , 2 ... n real imaginary real output = real imaginary real real imaginary ad9777 complex modulator frequency = c quadrature modulator frequency = q complex baseband signal rejected images dc e j( n + c + q )t ? 1 ? c ? q 1 + c + q 02706-082 figure 8 2 . i m age r e ject ion w i th mult i c ar ri er s i gn als
ad9777 rev. c | page 42 of 60 the complex carrier synthesized in the ad9777 digital modulator is accomplished by creating two real digital carriers in quadrature. carriers in quadrature cannot be created with the modulator running at f dac /2. as a result, complex modula- tion only functions with modulation rates of f dac /4 and f dac /8. region a and region b of figure 83 to figure 88 are the result of the complex signal described previously, when complex modulated in the ad9777 by +e jt . region c and region d are the result of the complex signal described previously, again with positive frequency components only, modulated in the ad9777 by ?e jt . the analog quadrature modulator after the ad9777 inherently modulates by +e jt . region a region a is a direct result of the upconversion of the complex signal near baseband. if viewed as a complex signal, only the images in region a remains. the complex signal a, consisting of positive frequency components only in the digital domain, has images in the positive odd nyquist zones (1, 3, 5, and so on), as well as images in the negative even nyquist zones. the appearance and rejection of images in every other nyquist zone becomes more apparent at the output of the quadrature modulator. the a images appear on the real and the imaginary outputs of the ad9777, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents the quadrature modulator lo and the horizontal scale now represents the frequency offset from this lo. region b region b is the image (complex conjugate) of region a. if a spectrum analyzer is used to view the real or imaginary dac outputs of the ad9777, region b appears in the spectrum. however, on the output of the quadrature modulator, region b is rejected. region c region c is most accurately described as a down conversion, as the modulating carrier is ?e jt . if viewed as a complex signal, only the images in region c remains. this image appears on the real and imaginary outputs of the ad9777, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents the quadrature modulator lo and the horizontal scale represents the frequency offset from this lo. region d region d is the image (complex conjugate) of region c. if a spectrum analyzer is used to view the real or imaginary dac outputs of the ad9777, region d appears in the spectrum. however, on the output of the quadrature modulator, region d is rejected. figure 89 to figure 96 show the measured response of the ad9777 and ad8345 given the complex input signal to the ad9777 in figure 89. the data in these graphs was taken with a data rate of 12.5 msps at the ad9777 inputs. the interpolation rate of 4 or 8 gives a dac output data rate of 50 msps or 100 msps. as a result, the high end of the dac output spectrum in these graphs is the first null point for the sin(x)/x roll-off, and the asymmetry of the dac output images is representative of the sin(x)/x roll-off over the spectrum. the internal pll was enabled for these results. in addition, a 35 mhz third-order low-pass filter was used at the ad9777/ ad8345 interface to suppress dac images. an important point can be made by looking at figure 91 and figure 93. figure 91 represents a group of positive frequencies modulated by complex +f dac /4, while figure 93 represents a group of negative frequencies modulated by complex ?f dac /4. when looking at the real or imaginary outputs of the ad9777, as shown in figure 91 and figure 93, the results look identical. however, the spectrum analyzer cannot show the phase relationship of these signals. the difference in phase between the two signals becomes apparent when they are applied to the ad8345 quadrature modulator, with the results shown in figure 92 and figure 94.
ad9777 rev. c | page 43 of 60 ? 100 ?80 ?60 ?40 ?20 0 0 ?0.5 ?1.5 ?1.0 ? 2.0 0.5 1.0 1.5 2.0 (lo) f out ( f data ) d a bc d a bc 02706-083 fig u re 8 3 . 2 int e r p ol at i o n, c o mp lex f da c /4 modu lat i on ? 100 ?80 ?60 ?40 ?20 0 0 ? 1.0 ?3.0 ? 2.0 ?4.0 1.0 2.0 3.0 4.0 (lo) f out ( f data ) d a b c da bc 02706-084 fig u re 8 4 . 4 int e r p ol at i o n, c o mp lex f da c /4 modu lat i on ? 100 ?80 ?60 ?40 ?20 0 0 ?2.0 ?6.0 ?4.0 ? 8.0 2.0 4.0 6.0 8.0 (lo) f out ( f data ) da b c da b c 02706-085 fig u re 8 5 . 8 int e r p ol at i o n, c o mp lex f da c /4 modu lat i on ? 100 ?8 0 ?6 0 ?4 0 ?2 0 0 0 ? 0.5 ?1.5 ? 1.0 ?2.0 0.5 1.0 1.5 2.0 (lo) f out ( f data ) da b c d a b c 02706-086 fig u re 8 6 . 2 int e r p ol at i o n, c o mp lex f da c /8 modu lat i on ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 0 ? 1.0 ? 3.0 ? 2.0 ?4.0 1.0 2.0 3.0 4.0 (lo) f out ( f data ) da b c d a b c 02706-087 fig u re 8 7 . 4 int e r p ol at i o n, c o mp lex f da c /8 modu lat i on ? 100 ?80 ?60 ?40 ?20 0 0 ?2.0 ?6.0 ?4.0 ? 8.0 2.0 4.0 6.0 8.0 (lo) f out ( f data ) da d a bc bc 02706-088 fig u re 8 8 . 8 int e r p ol at i o n, c o mp lex f da c /8 modu lat i on
ad9777 rev. c | page 44 of 60 01 0 2 0 3 0 4 0 5 0 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) frequency (mhz) 02706-089 fig u re 8 9 . a d 97 7 7 , r e al da c out p ut o f comp lex i n put si g n al ne ar bas e b a n d ( pos it iv e fr equen c i e s only ) , int e rp ol at ion = 4, n o m o d u l a t i o n i n a d 9 7 77 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 750 760 770 780 790 800 810 820 830 840 850 frequency (mhz) 02706-090 fi gur e 90 . ad9 777 co m p l e x output from figure 89, n o w quadrature mo dula te d by ad83 45 (lo = 800 m h z) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 0 1 02 03 0 4 0 5 0 frequency (mhz) 02706-091 fig u re 9 1 . a d 97 7 7 , r e al da c out p ut o f comp lex i n put si g n al ne ar bas e b a nd ( p os it iv e frequ e nc ies on ly ) , int e rpo l at io n = 4 , comp lex m o du lat i on in a d 97 77 = +f da c /4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 750 760 770 780 790 800 810 820 830 840 850 frequency (mhz) 02706-092 fi gur e 92 . ad9 777 co m p l e x output from figure 91, n o w quadrature mo dula te d by ad83 45 (lo = 800 m h z) ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 amp l itude (dbm) 0 1 02 03 0 4 0 5 0 frequency (mhz) 02706-093 fig u re 9 3 . a d 97 7 7 , r e al da c out p ut o f comp lex i n put si g n al ne ar baseb a nd (neg ativ e freq uen c ies only ), interp ol ati o n = 4 , comp lex m o du lat i on in a d 97 77 = ?f da c /4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 750 760 770 780 790 800 810 820 830 840 850 frequency (mhz) 02706-094 fi gur e 94 . ad9 777 co m p l e x output from figure 93, n o w quadrature mo dula te d by ad83 45 (lo = 800 m h z)
ad9777 rev. c | page 45 of 60 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 amp l itude (dbm) 0 2 0 4 0 6 0 8 0 100 frequency (mhz) 02706-095 fig u re 9 5 . a d 97 7 7 , r e al da c out p ut o f comp lex i n put si g n al ne ar bas e b a nd ( p os it iv e frequ e nc ies on ly ) , int e rpo l at io n = 8 , comp lex m o du lat i on in a d 97 77 = +f da c /8 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) 700 720 740 760 780 800 820 840 860 880 900 frequency (mhz) 02706-096 fi gur e 96 . ad9 777 co m p l e x output from figure 95, n o w quadrature mo dula te d by ad83 45 (lo = 800 m h z)
ad9777 rev. c | page 46 of 60 appl ying the output configura t ions the fol l o w in g s e c t io n s i l l u st ra te ty p i c a l o u t p u t co nf igura t io n s f o r th e ad9777. u n les s other w is e n o t e d , i t is ass u m e d tha t i ou tf s is s e t t o a n o m i na l 20 ma . f o r a p plica t ion s r e q u ir ing o p t i m u m d y namic p e r f o r ma n c e, a d i f f er en t i a l o u t p ut co nf igu- ra t i o n is s u g g e s te d . a si m p le dif f er en t i al o u t p u t ma y b e achie v e d b y co n v er t i n g i ou t a a nd i ou t b to a volt age out p ut b y t e rm i n a t i n g t h em t o a g nd v i a eq ual val u e r e s i s t o r s . t h i s t y pe o f co nf igur a t io n ma y b e us ef u l w h en dr i v in g a dif f er en t i a l vol t a g e i n p u t de vice such as a mo d u l a t o r . i f a co n v ersio n t o a sin g le-e nde d si g n a l is desir e d and t h e a p plic a t i o n a l lo ws fo r ac co u p ling, a n rf t r a n sfo r m e r ma y b e us ef u l ; if p o w e r ga in is r e q u ir e d , an o p a m p ma y be us e d . th e t r an sfo r m e r co nf igura - ti o n p r o v i d e s o p ti m u m hi gh f r eq ue n c y n o ise a n d d i st o r ti o n p e r f o r ma n c e. t h e dif f er en t i a l op a m p co nf igur a t io n is sui t a b le fo r a p plica t io n s r e q u ir in g dc cou p lin g , sig n a l g a in, and/o r le ve l s h i f tin g w i th in t h e ba n d w id t h o f th e ch osen o p a m p . a sin g le -e n d e d o u t p ut is sui t a b l e fo r a p plica t ion s r e q u ir ing a u n i p ol ar volt ag e out p ut . a p o s i t i ve u n i p ol ar out p ut volt age re su lt s i f i ou t a a nd/o r i ou t b is co nn e c te d to a lo ad r e sisto r , r lo a d , r e fer r e d t o a g nd . thi s co nf ig ura t io n is m o st sui t ab le fo r a sin g le- s u p ply sy stem r e quir ing a dc-cou ple d , g r o u nd r e fer r e d o u t p ut v o l t a g e. al ter n a t i v e l y , an a m pl if ier co u l d b e co nf igur e d as a n i-v con v er t e r , th us co n v er tin g i ou t a or i ou t b in t o a ne g a t i ve u n ip ol ar vol t age. thi s c o nf i g u r a t i o n pro v i d e s t h e b e st da c d c l i n e a r i t y a s i ou t a or i out b a r e m a in ta in e d a t gr o u n d o r v i r t u a l g r ou nd. unbuffered differ en tial ou tpu t , equivale nt circuit i n man y a p plic a t io n s , i t ma y b e n e cess a r y to underst a nd t h e eq ui valen t d a c o u t p u t c i r c ui t. this is es p e c i al l y us ef u l wh en desig n i n g o u t p ut f i l t ers o r w h e n dr i v in g in pu ts wi t h f i n i t e in p u t im p e dan c es. f i gur e 97 il l u s t ra t e s th e ou t p u t o f t h e ad9777 an d t h e e q ui v a len t c i r c ui t. a ty p i ca l a p plic a t ion w h e r e t h is info r m a t io n m a y b e us ef u l is w h e n desig n in g an i n t e r f ac e f i l t er betw een t h e ad9777 a nd t h e analog de vices ad8345 qu a d r a tu re mo du l a tor . i outa i outb v out + v out (differential) v source = i outfs (r a + r b ) p-p v out ? r a + r b 02706-097 figure 97. dac o u tput equivalent circ uit f o r t h e typ i cal s i t u a t io n, w h er e i ou tf s = 20 ma a nd r a a nd r b bo t h eq ual 50 ? , th e e q uivalen t cir c ui t val u es be co m e v so ur c e = 2 v p- p r ou t = 100 ? n o t e t h a t t h e ou t p ut im p e dan c e o f t h e ad977 7 d a c i t s e lf is g r e a t e r t h a n 10 0 k? a nd ty p i ca l l y has n o ef fe c t o n t h e im p e dan c e o f t h e e q ui v a len t ou t p ut cir c ui t. differential coupling using a trans f or mer an rf tra n sf o r m e r can be us e d t o p e r f o r m a dif f er en tial-t o - sin g le-e nde d si g n a l co n v ersion , as sho w n in f i gur e 98. a d i f f e r e n t i a l ly c o upl e d t r ans f or me r output prov i d e s t h e opt i m u m d i stor t i on p e r f or m a nc e f o r output s i g n a l s w h o s e sp e c t r a l c o n t e n t l i e s w i th i n th e t r a n s f o r m e r s pa s s b a n d . a n r f tra n sf o r m e r , s u c h as t h e m i ni-cir c u i t s t1-1 t , p r o v ides exce l l en t re j e c t i o n of c o m m o n - m o d e d i stor t i on ( t h a t i s , e v e n - o rd e r h a r m on i c s ) a n d noi s e o v e r a w i d e f r e q u e nc y r a nge. i t a l s o p r o v ide s e l e c t r i c a l is ol a t ion and t h e ab i l i t y t o de liv e r t w ic e t h e p o w e r t o t h e lo ad . t r a n sfo r m e rs wi t h dif f er en t i m p e dan c e ra t i o s ma y a l s o b e us e d fo r im p e dan c e ma tchin g p u r p o s es. mini-circuits t1-1t r load i outa i outb dac 02706-098 figure 9 8 . t r a n s f or me r-coup led o u tput circ uit the ce n t er t a p o n t h e p r ima r y side o f t h e t r a n s f o r m e r m u s t b e c o nne c te d to a g nd to prov i d e t h e ne c e ss ar y dc c u r r e n t p a t h fo r b o t h i ou t a a nd i ou t b . t h e c o m p l e me n t ar y volt age s a p p e ar i n g at i ou t a a nd i ou tb (tha t is, v ou t a a nd v ou t b ) swing symm etr i c a l l y a r o u n d a g n d a nd sh o u ld b e ma in t a i n e d wi t h in t h e sp e c if ie d o u t p u t co m p l i an ce ra n g e o f the ad9777. a dif f er en t i al r e sis t o r , r dif f , ca n b e in s e r t e d in a p pli c a t io n s w h er e t h e o u t p ut o f t h e t r a n sfo r m e r is co nn e c te d to t h e lo ad , r lo a d , v i a a p a ssi v e r e co n s tr ucti o n f i l t e r o r ca b l e . r dif f is det e r m i n e d b y t h e t r a n sfo r m e r s i m p e dan c e ra t i o a nd p r o v ides t h e p r o p er s o ur ce t e r m in a t io n t h a t r e su l t s i n a lo w v s w r . n o t e t h a t a p p r o x i- ma te l y half t h e sig n al p o w e r dissi p a t e s acr o s s r dif f .
ad9777 rev. c | page 47 of 60 differential coupling using an op am p an o p a m p c a n a l s o b e us e d to p e r f o r m a dif f er en t i a l - t o - sing le ende d con v ersi o n , as sh o w n i n f i gur e 99. this has t h e ad de d ben e f i t o f p r o v idin g s i g n al ga in as w e l l . i n f i gu r e 99, th e ad9777 is co nf igur ed wi t h tw o eq ual lo ad r e sist o r s, r lo a d , o f 25 ?. the dif f er en t i al v o l t a g e de v e l op e d acr o s s i ou t a a nd i ou t b is co n v er t e d t o a s i n g le -e n d e d sig n al v i a t h e dif f er en t i al o p a m p co nf igura t io n. an o p tio n al ca p a ci t o r can b e ins t al led acr o s s i ou t a a nd i ou t b , fo r m in g a r e a l p o le in a lo w-p a ss f i l t er . t h e a d d i t i o n of t h i s c a p a c i tor a l s o e n h a nc e s t h e op am p s d i s t or t i on p e r f or m a nc e b y pre v e n t i ng t h e d a c s f a s t sl e w i n g output f r om o v erlo ading t h e in p u t o f t h e o p a m p . i outa i outb c opt r opt 225 ? dac 225 ? 225 ? 500 ? 500 ? 25 ? 25 ? avdd ad8021 02706-099 figure 99. op a m p- co upled output circuit the co m m o n - m o d e (an d s e cond-o r der di sto r t i o n ) r e j e c t ion of t h is co nf igura t i o n is ty p i ca l l y d e t e r m i n e d b y t h e r e sist o r ma t c hing. th e o p a m p us e d m u s t o p era t e f r o m a d u al s u p p l y sin c e i t s ou t p u t is a p p r o x im a t e l y 1.0 v . a hig h sp e e d am plif ier , s u c h as t h e ad8021, ca p a b l e o f p r es er vin g t h e dif f er en tial p e r f o r ma n c e o f th e ad9777 while m e etin g o t h e r sys t em leve l ob jec t i v es (f o r e x a m p l e , cos t , p o w e r) is r e co mmended . th e o p a m p s dif f er en t i a l ga in, gain s e t t in g r e sist o r va l u es, a nd f u l l -s c a l e o u t p u t swin g ca p a b i li t i es sh o u l d al l be co n s ider ed w h en o p ti mi z i n g th i s ci r c ui t . r op t is ne cess a r y o n ly if le v e l shif t i n g is re qu i r e d on t h e op am p output . i n fi g u re 9 9 , a v dd , w h i c h i s th e p o si ti v e ana l og s u p p l y f o r bo th t h e ad9777 a nd t h e o p am p , is als o us ed t o lev e l s h if t t h e dif f er en tial o u t p u t o f th e ad9777 t o mids u p pl y (t ha t is, a v dd/2 ) . interfacing with the ad8345 quadrature modulator the ad9777 a r c h i t ec t u r e was def i n e d t o o p era t e in a tra n smi t s i g n a l ch ai n u s i n g an i m age re j e c t arch i t e c t u re. a qu a d r a t u re m o d u l a t o r is a l s o r e q u ir e d i n t h is a p plic a t ion and sh o u ld b e de s i g n e d to me e t t h e out p ut ch ar a c te r i st i c s of t h e d a c a s m u c h as p o s s i b le. th e ad8345 f r o m analog de vices m eets man y o f th e r e q u i r em en ts f o r i n t e rfa c i n g w i th t h e a d 9777. a s w i th a n y d a c o u t p u t in ter f ace , t h er e a r e a n u m b er o f is sues t h a t ha v e t o b e re s o lve d . t h e fol l o w ing s e c t i o ns l i st s o me of t h e ma j o r issu e s . dac compli ance volta g e/inpu t commo n-mode r a nge the d y na mic ran g e o f th e ad9 777 is o p timal when t h e d a c o u t p uts sw in g b e tw e e n 1.0 v . the i n p u t comm o n - m o d e ra ng e o f th e ad8345, a t 0.7 v , al lo ws o p tim u m d y namic ra n g e t o be a c h i ev e d in bo t h co m p o n en t s . gain/offset a d j u st the ma t c hi n g of t h e d a c o u t p u t t o t h e co mmo n - m o d e i n p u t o f th e ad8345 al lo ws t h e tw o c o m p on en ts t o b e dc-co u p l e d , w i t h no l e v e l s h i f t i ng ne c e ss ar y . t h e c o m b i n e d vo lt age of f s e t of th e tw o p a r t s can t h er ef o r e be c o m p en s a t e d via th e ad9777 p r og ra mma b l e o f fs et ad j u s t . this al lo ws exce l l e n t l o ca nce l la tion a t t h e ad8345 o u t p u t . the p r og ra mma b l e gain ad j u s t al lo ws f o r o p timal ima g e r e je c t io n as we l l . the ad9777 eval u a t io n bo a r d in c l udes a n ad8 345 a nd r e co mm ended in t e r f ac e (f igur e 105 a nd f i gur e 106). on t h e o u t p u t o f the ad9777, r9 an d r10 co n v er t t h e d a c o u t p u t c u r r en t t o a v o l t a g e . r16 ca n be us ed t o do a s l ig h t co mm on- m o de shif t if n e cess a r y . the (no w v o l t a g e) sig n a l is a p plie d t o a lo w-p a s s r e co n s t r uc t i o n f i l t er t o r e je c t d a c imag es. the co m p on en ts in stal led o n the ad9777 p r o v ide a 35 mh z c u t o f f b u t ca n b e change d to f i t t h e a pplica t ion. a b a lun (mini - cir c ui ts adtl1 - 12) is us ed t o c r os s th e g r o u n d p l a n e bounda r y t o th e ad8345. an o t h e r ba l u n ( m ini-cir c u i ts et c1-1-13) is us ed t o co u p le t h e l o in p u t o f t h e ad8345. the in t e r f ace r e q u ir es a lo w ac im p e dan c e r e t u r n p a th f r o m t h e ad8345, th er ef o r e a sin g l e co nnec t io n betw een t h e ad9 777 a nd ad834 5 g r o u n d plan es i s r e co mm e nde d. the p e r f o r ma nce o f th e ad977 7 a nd ad8345 in a n ima g e r e ject tra n smi t t e r , r e co n s tr ucti n g th r e e w c d m a ca rri e r s , ca n be s e en in f i gure 100. th e l o of th e ad8345 in this a p p l ica t io n is 800 mh z. i m a g e r e jec t io n (5 0 db) a nd l o f e ed thr o ug h ( ? 7 8 d b f s ) h a v e b e e n o p ti m i z e d w i th th e p r o g r a m m a b l e f e a t ur es o f the ad9777. the a v era g e o u t p u t p o w e r o f th e dig i tal w a ve for m for t h i s te st w a s s e t to ? 1 5 dbf s to a c c o u n t for t h e peak- t o -a v e ra g e ra ti o o f th e w c d m a si gn al . ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amp l itude (dbm) frequency (mhz) 782.5 762.5 802.5 822.5 842.5 02706-100 fi gur e 10 0 . ad9777 / a d8 34 5 synthe siz i ng a thre e-car r i e r wcd m a signa l at an lo of 8 0 0 mh z
ad9777 rev. c | page 48 of 60 evaluation board the ad9777 evaluation board allows easy configuration of the various modes, programmable via the spi port. software is available for programming the spi port from windows? 95, windows 98, or windows nt?/2000. the evaluation board also contains an ad8345 quadrature modulator and support circuitry that allows the user to optimally configure the ad9777 in an image reject transmit signal chain. figure 101 to figure 104 describe how to configure the evaluation board in the one-port and two-port input modes with the pll enabled and disabled. refer to figure 105 to figure 114, the schematics, and the layout for the ad9777 evaluation board for the jumper locations described below. the ad9777 outputs can be configured for various applications by referring to the following instructions. dac single-ended outputs remove transformers t2 and t3. solder jumper link jp4 or jp28 to look at the dac1 outputs. solder jumper link jp29 or jp30 to look at the dac2 outputs. jumpers 8 and 13 to 17 should remain unsoldered. jumpers jp35 to jp38 may be used to ground one of the dac outputs while the other is measured single-ended. optimum single-ended distortion performance is typically achieved in this manner. the outputs are taken from s3 and s4. dac differential outputs transformers t2 and t3 should be in place. note that the lower band of operation for these transformers is 300 khz to 500 khz. jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. the outputs are taken from s3 and s4. using the ad8345 remove transformers t2 and t3. jumpers jp4 and 28 to 30 should remain unsoldered. jumpers 13 to 16 should be soldered. the desired components for the low-pass interface filters l6, l7, c55, and c81 should be in place. the lo drive is connected to the ad8345 via j10 and the balun t4, and the ad8345 output is taken from j9.
ad9777 rev. c | page 49 of 60 signal generator clk+/clk? dataclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db15?db0 ad9777 dac2, db15?db0 40-pin ribbon cable jumper configuration for two port mode pll on jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02706-101 notes 1. to use pecl clock driver (u8), solder jp41 and jp42 and remove transformer t1. 2. in two-port mode, if dataclk/pll_lock is programmed to output pin 8, jp25 and jp39 should be soldered. if dataclk/pll_lock is programmed to output pin 53, jp46 and jp47 should be soldered. see the two port data input mode section for more information. fig u re 1 01. tes t c o nf ig urat ion f o r a d 97 77 in tw o-p o rt m o de wi th p ll enabl e d si gnal ge ner a to r frequency = input da ta ra te, dac output da ta ra te = si gna l gene rato r fr equen c y i n terpo l at ion r a te signal generator clk+/clk? oneportclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db15?db0 ad9777 dac2, db15?db0 jumper configuration for one port mode pll on jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02706-102 notes 1. to use pecl clock driver (u8), solder jp41 and jp42 and remove transformer t1. fig u re 1 02. tes t c o nf ig urat ion f o r a d 97 77 in one- po rt m o de wit h pll e n a b led, s i g n al g e ne r a t o r frequ e ncy = o n e-h a lf int e r l e a v e d input dat a r at e, onep ortclk = int e rlea ved input da t a ra te, dac output da ta r a te = s i gn al g e ne rat o r f r equ e ncy inte rpo l at io n r a te
ad9777 rev. c | page 50 of 60 signal generator clk+/clk? dataclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db15?db0 ad9777 dac2, db15?db0 40-pin ribbon cable jumper configuration for two port mode pll off jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02706-103 notes 1. to use pecl clock driver (u8), solder jp41 and jp42 and remove transformer t1. 2. in two-port mode, if dataclk/pll_lock is programmed to output pin 8, jp25 and jp39 should be soldered. if dataclk/pll_lock is programmed to output pin 53, jp46 and jp47 should be soldered. see the two port data input mode section for more information. fig u re 1 03. tes t c o nf ig urat ion f o r a d 97 77 in tw o-p o rt m o de wit h pll d i sabled, dac output data r a te = si gnal genera tor frequency , dataclk = sign al gener a tor fr equency/ interp ol a t io n r a te signal generator clk+/clk? oneportclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db15 ? db0 ad9777 dac2, db15 ? db0 jumper configuration for one port mode pll off jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02706-104 notes 1. to use pecl clock driver (u8), solder jp41 and jp42 and remove transformer t1. fig u re 1 04. tes t c o nf ig urat ion f o r a d 97 77 in one- po rt m o de wit h pll d i sabled, dac output data r a te = si gnal genera tor frequency , oneportclk = int e rleaved input d a t a rate = 2 si gna l genera tor frequency/ interp ol a t io n r a te.
ad9777 rev. c | page 51 of 60 jp21 jp7 c5 4 dnp r2 8 0 ? r2 6 1k ? r3 5 51 ? r3 6 51 ? jp20 c7 9 dnp r3 2 51 ? r3 4 dnp c6 9 0.1 f c6 3 16v 22 f clkv dd_ in j7 tp6 re d tp7 blk c6 2 16v 22 f clkv dd l1 ferrite r3 3 51 ? c7 8 0.1 f jp18 v ddm c7 2 10v 10 f c7 5 0.1 f o2n o2p o1n o1p jp19 v ddm c7 4 100pf c3 5 100pf v ddm c7 6 100pf c7 7 100pf r3 0 dnp j10 dgnd2 ; 3 , 4 , 5 j9 dgnd2 ; 3 , 4 , 5 j3 cgnd ad8345 u2 2 2 2 2 2 r c 0603 r c 0603 r c 0603 r c 0603 r c 0603 r c 0603 c c 0603 r c 0603 r c 0603 l c 1210 r c 0603 c c 0603 bcase c c 0603 c c 0603 c c 0603 r c 0603 g2 e nbl vps1 g1a g1b loip vps2 g4a g4b qbbp vou t g3 ibbp ibbn loin local os c inp u t modulate d outp ut power input filters l c 0805 l6 dnp l c 0805 l7 dnp l4 dnp l5 dnp jp11 c c 0805 dcase dcase c c 0805 t6 6 adtl1-12 p s 4 31 2 2 c8 0 dnp c c 0603 r3 7 dnp c7 3 dnp c c 0805 c c 0805 l c 0805 l c 0805 2 c c 0603 qbbn r2 3 0 ? c c 0805 c8 1 dnp c5 5 dnp 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 t4 5 e t c1 -1 -1 3 sp 4 3 1 t5 3 adtl1-12 s p 1 64 c c 0603 jp43 jp45 2 jp44 c6 8 0.1 f c6 4 16v 22 f av dd_ in j6 tp4 re d tp5 blk c6 1 16v 22 f av dd j4 agnd l c 1210 jp10 jp9 c c 0805 dcase dcase l2 ferrite c6 7 0.1 f c6 5 16v 22 f dv dd_ in j5 tp2 re d tp3 blk c6 6 16v 22 f dv dd l3 ferrite j8 dgnd l c 1210 c c 0805 dcase dcase c3 2 0.1 f c2 8 16v 22 f v ddmin w1 2 l8 ferrite w1 1 dgnd2 l c 1210 c c 0805 dcase 02706-105 c + + + + + + + + fi gur e 10 5 . ad8345 cir c ui tr y o n ad9 7 7 7 eval ua ti on bo ard
ad9777 rev. c | page 52 of 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dvdd c c c r2 1k ? r3 1k ? clkv dd dv dd rc0603 rc0603 bcas e bcas e cc0603 cc0603 cc0603 cc0603 rc0603 tp 15 wht t1 t1-1t tp 14 wht r1 200 ? r40 5k ? r5 49. 9 ? r39 1k ? c13 0. 1 f c1 10 f 6. 3v c10 10 f 6. 3v c26 0. 001 f c12 0. 1 f c11 0. 1 f c42 0. 1 f cc0603 cc0805 c27 1pf c36 0. 1 f cc0805 c37 0. 1 f cc0805 c38 0. 1 f cc0805 c39 0. 1 f cc0805 c40 0. 1 f cc0805 c41 0. 1 f + + c jp 22 jp 23 jp 33 jp 1 clkp clkn r38 10k ? jp 2 s1 s2 s6 12 11 13 iq iq s5 u4 adclk dv dd clkin aclkx cgnd; 3, 4, 5 dgnd; 3, 4, 5 dataclk jp 39 jp 24 jp 5 bd15 bd14 op clk_3 opclk 74v cx 86 opclk dgnd; 3, 4, 5 dgnd; 7 dv dd; 14 agnd; 3, 4, 5 jp 27 jp 40 jp 34 jp 32 jp 26 jp 31 jp 3 cx 2 74v cx 86 12 13 11 u3 dv dd; 14 dv dd dgnd; 7 cx 1 jp 25 jp 12 cx 3 6 5 4 1 2 3 rc0603 cc0603 bcas e c9 10 f 6. 3v c25 0. 001 f + dv dd cc0603 bcas e c8 10 f 6. 3v c24 0. 001 f + dv dd cc0603 bcas e c7 10 f 6. 3v c23 0. 001 f + dv dd cc0603 cc0605 cc0805 rc0603 c29 0. 1 f c45 0. 01 f ad15 v ddc1 v dda6 vssa 1 0 v dda5 vssa 9 v dda4 vssa 8 vssa 7 iout1 p iout1 n vssa 6 vssa 5 iout2 p iout2 n vssa 4 vssa 3 v dda3 vssa 2 vssa 1 vssd 6 v ddd6 p2 d 0 p2 d 1 p2 d 2 p2 d 3 p2 d 4 p2 d 5 p2 d 6 p2 d 7 vssd 5 v ddd5 v dda2 v dda1 fs adj1 fs adj2 re fout r eset sp- c s b sp- c l k sp- sd i sp- sd o lf v ddc2 vssc 1 clkp clkn vssc 2 dclk-p lll vssd 1 v ddd1 p1 d 1 5 p1 d 1 4 p1 d 1 3 p1 d 1 2 p1 d 1 1 p1 d 1 0 vssd 2 v ddd2 p1 d 9 p1 d 8 p1 d 7 p1 d 6 p1 d 5 p1 d 4 vssd 3 v ddd3 p1 d 3 p1 d 2 p1 d 1 p1 d 0 p2 d 1 5 - iqsel p 2 d14-o p clk p2 d 1 3 p2 d 1 2 p2 d 1 1 p2 d 1 0 p2 d 9 p2 d 8 vssd 4 v ddd4 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 bd13 bd12 bd11 bd10 bd09 bd08 a d 9777+tsp u1 c20 0. 1 f cc0603 c19 0. 1 f cc0603 cc0603 cc0603 cc0603 cc0603 rc1206 c14 0. 1 f bcas e cc0603 c2 10 f 6. 3 v + c18 0. 1 f cc0603 bcas e c17 0. 1 f c16 0. 1 f cc0603 c21 0. 001 f cc0603 cc0603 c15 0. 1 f bcas e cc0805 c3 10 f 6. 3 v c4 10 f 6. 3v r7 2k ? 0. 01% r8 1k ? 0. 01% + + bcas e c5 10 f 6. 3v + c58 dnp c58 dnp c57 dnp c59 dnp r6 1k ? av dd av dd dv dd cc0603 c22 0. 001 f bcas e c6 10 f 6. 3v + dv dd tp 11 wht tp 10 wht tp 9 wht tp 8 wht spc sp spc l k spsd i spsd o bd00 bd01 bd02 bd03 bd04 bd05 bd06 bd07 r10 51k ? r9 51k ? r16 10k ? r42 49. 9k ? r43 49. 9k ? rc0603 rc0603 rc0603 rc1206 cc0603 c70 0. 1 f jp 8 jp 4 jp 28 jp 13 jp 15 jp 16 jp 14 jp 36 jp 38 jp 17 jp 29 jp 30 agnd; 3, 4, 5 t3 out 2 j37 j35 3 t2 s3 o1 n o1 p o2 n o2 p s4 out1 agnd; 3, 4, 5 t1-1t 2 1 4 5 6 3 t1-1t 2 1 8 9 10 4 5 6 c70 0. 1 f r12 51k ? r11 51k ? r17 10k ? rc0603 rc0603 rc0603 cc0603 iq spsd o jp 46 jp 47 u4 dv dd; 14 dgnd; 7 74v cx 86 02706- 106 fi gur e 10 6 . ad9777 clo c k, po wer suppl i e s, a n d output ci r c ui tr y
ad9777 rev. c | page 53 of 60 02706-107 j clk k clr pr e q q 74lc x 112 u7 agnd; 8 dv dd; 1 6 c5 2 4.7 f 6.3v dv dd c5 3 0.1 f cc0805 acas e 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-a ribbon j1 2 1 3 45 678 9 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 345 67 89 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp 8 dnp rp 6 50 ? 2 1 3 45 678 9 1 0 2 1 345 67 89 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp 7 dnp rp 5 50 ? ad1 5 ad1 4 ad1 3 ad1 2 ad1 1 ad1 0 ad0 9 ad0 8 ad0 7 ad0 6 ad0 5 ad0 4 ad0 3 ad0 2 ad0 1 ad0 0 11 6 21 5 31 4 41 3 51 2 61 1 71 0 89 11 6 21 5 31 4 41 3 51 2 61 1 71 0 89 rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 1 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? rp 2 22 ? r1 5 220 ? rc1206 adclk 74vc x 86 j clk k clr pr e q q dv dd op clk_ 2 dv dd; 1 4 agnd; 7 74lc x 112 u7 opclk u4 2 3 1 op clk_ 3 3 1 2 5 4 10 14 11 12 13 9 7 15 6 c3 1 4.7 f 6.3v dv dd c3 4 0.1 f cc0805 acas e c3 0 4.7 f 6.3v dv dd c3 3 0.1 f cc0805 acas e 74vc x 86 dv dd; 1 4 agnd; 7 u4 5 6 4 74vc x 86 dv dd; 1 4 agnd; 7 u3 2 3 1 74vc x 86 dv dd; 1 4 agnd; 7 u3 5 6 4 74vc x 86 dv dd; 1 4 agnd; 7 u3 10 8 9 cx 2 cx 3 cx 1 + + + fi gur e 10 7 . ad9777 eva l ua tio n boa r d input (a cha n nel ) a n d cl oc k buffe r cir c ui t r y
ad9777 rev. c | page 54 of 60 02706-108 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-b ribbon j2 2 1 3 4 567 89 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 3 45 67 8 9 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp 1 0 dnp rp 1 1 50 ? 2 1 3 4 567 89 1 0 2 1 3 45 67 8 9 1 0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp 9 dnp rp 1 2 50 ? bd1 5 bd1 4 bd1 3 bd1 2 bd1 1 bd1 0 bd0 9 bd0 8 bd0 7 bd0 6 bd0 5 bd0 4 bd0 3 bd0 2 bd0 1 bd0 0 11 6 21 5 31 4 41 3 51 2 61 1 71 0 89 11 6 21 5 31 4 41 3 51 2 61 1 71 0 89 r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 3 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r p 4 22 ? r2 1 dnp clkv dd cgnd; 5 clkv dd; 8 aclkx r1 3 120 ? r4 120 ? r1 8 200 ? r1 4 200 ? r c 0805 m c 100ept22 r c 0805 r c 0805 r c 0805 c4 3 4.7 f 6.3v dv dd c5 1 0.1 f c4 4 4.7 f 6.3v dv dd dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 1 2 dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 12 13 dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 43 dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 10 11 dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 65 dgnd; 7 dv dd; 1 4 u5 7 4 ac1 4 89 1 2 3 4 5 6 spi por t p1 spc sb spc lk spsd i spsd o dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 1 2 dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 13 12 dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 3 4 dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 11 10 dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 5 6 dgnd; 7 dv dd; 1 4 u6 7 4 ac1 4 9 8 r5 0 9k ? r4 8 9k ? r4 5 9k ? r c 0805 r c 0805 r c 0805 acase c c 805 acase c5 0 0.1 f c c 805 c6 0 0.1 f c4 9 4.7 f 6.3v clkdd acase cc8 0 5 4 3 6 u8 2 1 7 u8 c c 805 c4 7 1nf c c 805 jp41 jp42 c4 6 0.1 f r2 0 dnp r c 0805 r2 2 dnp r2 4 dnp r c 0805 r c 0805 r c 0805 c c 805 c4 8 1nf clkv dd; 8 cgnd; 5 m c 100ept22 clkv dd clkv dd clkn clkp + c c c c c c c + + r1 9 100 ? fi gur e 10 8 . ad9777 eva l ua tio n boa r d input (b cha n ne l ) a n d sp i p o r t cir c ui tr y
ad9777 rev. c | page 55 of 60 02706-109 fi gur e 10 9 . ad9777 eva l ua tio n boa r d com p o n e n ts, to p si de 02706-110 fi gur e 11 0 . ad9777 eva l ua tio n boa r d com p o n e n ts, bo tto m si de
ad9777 rev. c | page 56 of 60 02706-111 fi gur e 11 1 . ad9777 eva l ua tio n boa r d la yo ut, la yer one (to p ) 02706-112 fi gur e 11 2 . ad9777 eva l ua tio n boa r d la yo ut, la yer two (gr o und pl a n e )
ad9777 rev. c | page 57 of 60 02706-113 fi gur e 11 3 . ad9777 eva l ua tio n boa r d la yo ut, la yer thr e e (po w er p l a n e ) 02706-114 fi gur e 11 4 . ad9777 eva l ua tio n boa r d la yo ut, la yer four (bo ttom )
ad9777 rev. c | page 58 of 60 outline dimensions compliant to jedec standards ms-026-add-hd 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.00 bsc sq bottom view (pins up) exposed pad figure 115. 80-lead thin quad fl at p a ck ag e, e x pos e d p a d [tqf p_e p ] (sv - 80-1) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model t e mper a t ur e r a nge p a ck age descri ption p a ck age o p tion ad9777bsv ?40c to +85c 80-l e ad thin quad f l a t p a ck ag e , exposed p a d [ t qfp_ep] sv -80-1 AD9777BSVRL ?40c to +85c 80-l e ad thin quad f l a t p a ck ag e , exposed p a d [ t qfp_ep] sv -80-1 ad9777bsvz 1 ?40c to +85c 80-l e ad thin quad f l a t p a ck ag e , exposed p a d [ t qfp_ep] sv -80-1 ad9777bszvrl 1 ?40c to +85c 80-l e ad thin quad f l a t p a ck ag e , exposed p a d [ t qfp_ep] sv -80-1 a d 9 7 7 7 - e b e v alua t i o n boar d 1 z = pb-free part.
ad9777 rev. c | page 59 of 60 notes
ad9777 rev. c | page 60 of 60 ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02706-0-1 /06 (c) notes

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